Research institute Leti and low-volume wafer service CMP are cooperating on a project to let fabless chipmakers explore the use of non-volatile resistive RAMs in their designs.
Research institute Leti and Soitec have decided to team up to work on a new generation of engineered substrates, such as specialized SOI wafers.
Fifteen years on from the design gap that triggered the IP revolution, implementation costs have created a new one.
Imec proposes using stacked CMOS transistors and buried power rails to improve density for the 3nm process node.
For nVidia chief scientist and Stanford professor Bill Dally, now is a great time to be involved in hardware design, thanks to the rise of AI.
Panasonic and AIST have turned a resistive memory (RRAM) into a hydrogen sensor that they claim works at much lower energy than existing designs.
Researchers from the UC Berkeley and Intel teamed up to develop an energy-tuneable RF front-end on a digital finFET process with no need for analog process options.
Imec will at this week’s VLSI Symposia describe how it fabricated a form of magnetic memory suitable for use as a non-volatile cache onto 300mm wafers using CMOS-compatible processes.
Imec and Unisantis Electronics have developed a process flow based on a vertical transistor with a gate on all sides they claim will lead to denser memories on a 5nm node.
The circuits sessions at mid-June's VLSI Symposia in Honolulu feature a number of papers that improve the performance of scaled mixed-signal processes.
View All Sponsors