Research Groups

June 27, 2018

Remember the design gap? It’s back

Fifteen years on from the design gap that triggered the IP revolution, implementation costs have created a new one.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: , ,
June 22, 2018

Imec stacks transistors for denser 3nm option

Imec proposes using stacked CMOS transistors and buried power rails to improve density for the 3nm process node.
Article  |  Topics: Blog Topics  |  Tags: , , , , ,   |  Organizations:
June 21, 2018

AI is all about low-energy hardware says Dally

For nVidia chief scientist and Stanford professor Bill Dally, now is a great time to be involved in hardware design, thanks to the rise of AI.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , , , ,   |  Organizations: ,
June 21, 2018

RRAM to sniff out hydrogen from fuel cells

Panasonic and AIST have turned a resistive memory (RRAM) into a hydrogen sensor that they claim works at much lower energy than existing designs.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations: ,
June 20, 2018

SAR-VCO combo tunes RF receiver power on 16nm

Researchers from the UC Berkeley and Intel teamed up to develop an energy-tuneable RF front-end on a digital finFET process with no need for analog process options.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: ,
June 18, 2018

Switch to orbit mode boosts MRAM on 300mm wafers

Imec will at this week’s VLSI Symposia describe how it fabricated a form of magnetic memory suitable for use as a non-volatile cache onto 300mm wafers using CMOS-compatible processes.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
May 23, 2018

Pillar transistor points to smaller SRAMs at 5nm

Imec and Unisantis Electronics have developed a process flow based on a vertical transistor with a gate on all sides they claim will lead to denser memories on a 5nm node.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:
May 11, 2018

Mixed-signal circuits push scaled CMOS at VLSI

The circuits sessions at mid-June's VLSI Symposia in Honolulu feature a number of papers that improve the performance of scaled mixed-signal processes.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: , ,
May 4, 2018

7nm process with EUV to feature at VLSI

Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
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April 9, 2018

DAC keynotes and sessions aim for AI

DAC in June will feature a series of keynotes and technical sessions on machine learning and AI for both target applications and in the design process itself.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations: , , ,

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