Research Groups

October 18, 2021

Three ways to 3D feature at IEDM

Three highlighted papers at IEDM, taking place in December, show the different approaches to the use of the vertical dimension to cut energy use and improve density.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: , , ,
September 24, 2021

Siemens brings chip-design flow to DARPA Toolbox Initiative

Siemens EDA has become the first of the major EDA vendors to join the DARPA Toolbox Initiative.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations: , , , ,
June 15, 2021

Imec cuts transistor gap to less than 20nm with forksheets

Imec showed at VLSI Symposia a process flow that can cut the gap between complementary transistors to less than 20nm.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
June 14, 2021

AI’s design speedups, with and without machine learning

At the VLSI Symposia, researchers described how AI hardware could help dramatically accelerate analog and digital design and not all of it directly through machine learning.
May 2, 2021

Alternative scaling approaches form VLSI 2021 technology highlights

The upcoming VLSI Symposia will feature a number of papers that show the ways in which novel approaches are going to be needed to continue scaling.
January 15, 2021

Copper’s future is troubled but it’s likely to stick around

The metal has done sterling service for 20 years but the time is approaching to find a replacement for copper as problems with parasitics continue to build up, work presented at last month’s IEDM shows. But it's not an obvious switch.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: , , , ,
December 21, 2020

Plasmonics may point way to faster interchip comms

Work by the University of Toronto and Arm presented at IEDM indicates plasmonics could be a viable contender for high-speed chip-chip communications.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , ,   |  Organizations: ,
December 18, 2020

Backside metal defends against IR drop and side-channel attacks

Work presented at IEDM 2020 shows taking advantage of the IC backside for power and ground for the additional area can deliver further benefits for IR drop and security.
December 15, 2020

Chipmaking’s new environment presented at IEDM

Imec's senior vice president of CMOS outlined future directions for the technology over the coming decade.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
December 4, 2020

Analog surges as cause of IC respins (Wilson Functional Verification 2020 – Part Three)

Study may point to new challenges in more bidirectional AMS implementations on SoC-class designs, though formal and emulation help keep respin count in check.

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