Research Groups

Imec has developed cleaner techniques for preparing die-to-wafer bonding components for high-density logic-memory stacks and optical integration.

This year’s ECTC, held at the end of May, will continue its focus on the role of packaging in keeping silicon scaling on track.

The upcoming VLSI Symposium will examine progress in using backside contacts and 3D structures to improve density and speed as well as continuing improvements to finFET processes.

Shifting to low-carbon generation for electricity would do much to cut the carbon footprint of semiconductor processes according to work shown at this year’s IEDM.

At IEDM, CEA-Leti described a process that avoids the thermal problems of implementing CMOS transistors in the metal stack using monolithic integration.

Applied Materials and CEA-Leti have expanded their collaboration with the creation of a joint lab to develop materials useful for sensors, RF communications, and power devices, and with a focus on heterogeneous integration.

Imec has a version of its imec.netzero virtual fab tool accessible to the general public with the aim of showing the environmental impact of IC manufacturing.

Codasip has put support for a set of instruction extensions intended to secure memory into its RISC-V core designs.

Backside power delivery could lead to improvements in chip density and more straightforward place-and-route phases according to work presented at this year’s VLSI Symposium.

Ferroelectric memory may be able to stage a comeback thanks to materials innovations as work presented at VLSI Symposium have shown, though there is still plenty to do.