Digital/analog implementation

A new paper looks at examples for using The Boundary Condition Independent Reduced Order Model (BCI-ROM) in its VHDL-AMS implementation for electro-thermal analysis.

Just how much of the flow has already has 'shift left' benefit and what is fueling further progress.

Calibre Design Enhancer moves physical verification checks and automated DRC-clean via and cell insertion into P&R

Three fast developing AI techniques underpin the efficiencies in the new Solido custom design and verification platform.

The company says the mixed-signal platform enabled a 5X improvement in verification productivity.

The design and verification IP specialist will present its full range, including the Smart Compiler, at next week's Design Automation Conference.

DAC 2021 is looming and here is our first round up of a major EDA player's plans for the physical event in San Francisco.

Learn how Calibre RealTime Digital allows you to identify, explore and fix DRC violations as you go.

A case study describes how the RF and AMS specialist achieved efficiencies on a complex server DSP SoC project by running as-you-go DRC during place and route.

The free-to-attend user meetings for Mentor clients will retain the same format mixing technical presentations with keynotes and networking.