The design and verification IP specialist will present its full range, including the Smart Compiler, at next week's Design Automation Conference.
DAC 2021 is looming and here is our first round up of a major EDA player's plans for the physical event in San Francisco.
Learn how Calibre RealTime Digital allows you to identify, explore and fix DRC violations as you go.
A case study describes how the RF and AMS specialist achieved efficiencies on a complex server DSP SoC project by running as-you-go DRC during place and route.
The free-to-attend user meetings for Mentor clients will retain the same format mixing technical presentations with keynotes and networking.
Mentor adds Analog FastSPICE eXTreme innovations for designs facing increasing parasitic complexity and contact resistance challenges at cutting edge nodes.
Live and on-demand videos as well as You Tube 'tips and techniques' clips form part of a wide 'work at home' support package from Mentor.
Updates to existing designs are often error-prone, though safety tolerances are necessarily tightening. This four-step strategy can help.
Traditional approaches to via insertion to meet reliability and yield at advanced nodes are giving way to necessary automation.
Emulation is already playing a vital role in advanced automotive design within a digital twin environment.
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