Digital/analog implementation

August 8, 2023

Catch up with the state-of-the-art in ‘shift left’

Just how much of the flow has already has 'shift left' benefit and what is fueling further progress.
July 10, 2023

Calibre ‘shifts left’ into place and route

Calibre Design Enhancer moves physical verification checks and automated DRC-clean via and cell insertion into P&R
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July 10, 2023

Siemens fuels custom IC flows with artificial intelligence

Three fast developing AI techniques underpin the efficiencies in the new Solido custom design and verification platform.
April 25, 2023

Alps Alpine composes capacitance IC with Symphony

The company says the mixed-signal platform enabled a 5X improvement in verification productivity.
December 3, 2021

DAC 2021 preview: SmartDV

The design and verification IP specialist will present its full range, including the Smart Compiler, at next week's Design Automation Conference.
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November 23, 2021

DAC 2021 Preview: Siemens EDA

DAC 2021 is looming and here is our first round up of a major EDA player's plans for the physical event in San Francisco.
June 21, 2021

From iterative to in-design DRC and debug for place and route

Learn how Calibre RealTime Digital allows you to identify, explore and fix DRC violations as you go.
May 14, 2021

How MaxLinear cut physical verification time with in-design DRC

A case study describes how the RF and AMS specialist achieved efficiencies on a complex server DSP SoC project by running as-you-go DRC during place and route.
October 29, 2020

User2User sets virtual 2020 dates: US in November, Europe in December

The free-to-attend user meetings for Mentor clients will retain the same format mixing technical presentations with keynotes and networking.
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July 20, 2020

FastSPICE upgrade boosts nano-scale analog verification by up to 10X

Mentor adds Analog FastSPICE eXTreme innovations for designs facing increasing parasitic complexity and contact resistance challenges at cutting edge nodes.
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