3nm

The organizers of the 66th annual IEDM have decided to hold the December conference virtually.

As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.

AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.

The IEDM has chosen a theme based around technologies for connected devices for its upcoming conference in December.

CMOS moving to 3nm and DRAM going beyond 20nm scaling are two of the late papers at the upcoming IEDM and part of a larger examination of semiconductor trends.

Imec proposes using stacked CMOS transistors and buried power rails to improve density for the 3nm process node.

Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.

Innovation and advances in EUV and OPC lead Mentor's offerings at SPIE in San Jose later this month.

DTCO work by GlobalFoundries and Qualcomm reported at VLSI Symposia shows the need to minimize fin counts in future finFET processes.