3nm

May 2, 2024

VLSI to explore vertical device changes and 3nm finFET

The upcoming VLSI Symposium will examine progress in using backside contacts and 3D structures to improve density and speed as well as continuing improvements to finFET processes.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: , ,
June 15, 2021

Imec cuts transistor gap to less than 20nm with forksheets

Imec showed at VLSI Symposia a process flow that can cut the gap between complementary transistors to less than 20nm.
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June 3, 2021

Three libraries tune speed and density on TSMC’s 3nm process

TSMC will provide three different standard-cell libraries for its upcoming finFET-based 3nm process to cover requirements from high-density mobile to high-performance computing, allowing tradeoffs for area and circuit frequency.
Article  |  Topics: Blog - EDA, - HPC, Blog - IP  |  Tags: , ,   |  Organizations:
January 15, 2021

Copper’s future is troubled but it’s likely to stick around

The metal has done sterling service for 20 years but the time is approaching to find a replacement for copper as problems with parasitics continue to build up, work presented at last month’s IEDM shows. But it's not an obvious switch.
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December 15, 2020

Chipmaking’s new environment presented at IEDM

Imec's senior vice president of CMOS outlined future directions for the technology over the coming decade.
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August 25, 2020

TSMC fills in sub-nodes as EUV gains ground

TSMC is using its growing experience with EUV lithography to fill in sub-nodes between its major releases as it prepares to extend finFET technology to the forthcoming N3 process.
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June 24, 2020

IEDM switches to virtual format for 2020

The organizers of the 66th annual IEDM have decided to hold the December conference virtually.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,
June 16, 2020

Transistor stacks piled high at VLSI

As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.
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June 15, 2020

EDA in the cloud boosts DRC iterations for AMD

AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.
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September 4, 2019

IEDM homes in on connected devices

The IEDM has chosen a theme based around technologies for connected devices for its upcoming conference in December.
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