3nm

The upcoming VLSI Symposium will examine progress in using backside contacts and 3D structures to improve density and speed as well as continuing improvements to finFET processes.

Imec showed at VLSI Symposia a process flow that can cut the gap between complementary transistors to less than 20nm.

TSMC will provide three different standard-cell libraries for its upcoming finFET-based 3nm process to cover requirements from high-density mobile to high-performance computing, allowing tradeoffs for area and circuit frequency.

The metal has done sterling service for 20 years but the time is approaching to find a replacement for copper as problems with parasitics continue to build up, work presented at last month’s IEDM shows. But it's not an obvious switch.

Imec's senior vice president of CMOS outlined future directions for the technology over the coming decade.

TSMC is using its growing experience with EUV lithography to fill in sub-nodes between its major releases as it prepares to extend finFET technology to the forthcoming N3 process.

The organizers of the 66th annual IEDM have decided to hold the December conference virtually.

As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.

AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.

The IEDM has chosen a theme based around technologies for connected devices for its upcoming conference in December.