Research Groups

Embedded magnetic RAM is emerging as a contender for on-chip memory not just from a density standpoint but from that of power.

CEA-Leti claimed at IEDM to have achieved major steps in bringing monolithic 3D integration closer to production readiness.

CMOS moving to 3nm and DRAM going beyond 20nm scaling are two of the late papers at the upcoming IEDM and part of a larger examination of semiconductor trends.

The latest Mentor-commissioned Wilson Research Group study on ASIC and FPGA verification highlights technique adoption and maturity.

The LightSuite Compiler produces designs based on Python descriptions and certifies them DRC-clean through hooks into the market-leading Calibre DFM suite.

Research institute Leti and low-volume wafer service CMP are cooperating on a project to let fabless chipmakers explore the use of non-volatile resistive RAMs in their designs.

Research institute Leti and Soitec have decided to team up to work on a new generation of engineered substrates, such as specialized SOI wafers.

Fifteen years on from the design gap that triggered the IP revolution, implementation costs have created a new one.

Imec proposes using stacked CMOS transistors and buried power rails to improve density for the 3nm process node.

For nVidia chief scientist and Stanford professor Bill Dally, now is a great time to be involved in hardware design, thanks to the rise of AI.