The circuits sessions at mid-June's VLSI Symposia in Honolulu feature a number of papers that improve the performance of scaled mixed-signal processes.
Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
DAC in June will feature a series of keynotes and technical sessions on machine learning and AI for both target applications and in the design process itself.
PDK enables photonics prototyping on MPW runs and compatibility with volume production at STMicroelectronics at Crolles.
Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
Two leading European research institutes presented their work on the feasibility and cost-effectiveness of monolithic 3D integration at this year's IEDM.
Intel and GlobalFoundries will talk about their post-14nm finFET-based processes at December's IEDM.
DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.
The major West Coast technical conference for lithography is just two weeks away and offers a packed agenda.
IMEC has claimed at IEDM to have implemented for the first time the CMOS integration of vertically stacked nanowire transistors.
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