Research Groups

May 4, 2018

7nm process with EUV to feature at VLSI

Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: , , ,
April 9, 2018

DAC keynotes and sessions aim for AI

DAC in June will feature a series of keynotes and technical sessions on machine learning and AI for both target applications and in the design process itself.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations: , , ,
April 5, 2018

Leti releases photonics design kit for Synopsys PhoeniX OptoDesigner suite

PDK enables photonics prototyping on MPW runs and compatibility with volume production at STMicroelectronics at Crolles.
Article  |  Topics: Blog - EDA, IP, - Product  |  Tags: , ,   |  Organizations: , ,
February 28, 2018

Cadence and Imec tape out 3nm interconnect test chip

Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
December 6, 2017

European teams explore 3D integration tradeoffs

Two leading European research institutes presented their work on the feasibility and cost-effectiveness of monolithic 3D integration at this year's IEDM.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations: ,
October 18, 2017

Sub-10nm finFETs to feature at IEDM

Intel and GlobalFoundries will talk about their post-14nm finFET-based processes at December's IEDM.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: , , ,
May 2, 2017

Wally Rhines looks beyond ‘endless verification’ to the system era

DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.
February 13, 2017

SPIE Advanced Lithography preview: Mentor Graphics

The major West Coast technical conference for lithography is just two weeks away and offers a packed agenda.
December 7, 2016

IMEC stacks nanowire transistors together on CMOS

IMEC has claimed at IEDM to have implemented for the first time the CMOS integration of vertically stacked nanowire transistors.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
December 7, 2016

Overcoming electromigration analysis limitations for larger on-die power grids

Award-winning paper describes new strategy offering both greater speed and accuracy.
Article  |  Topics: Blog Topics  |  Tags: , , ,   |  Organizations: , ,

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