Real Intent tool looks at paths to hardware vulnerability
Real Intent has developed a tool for identifying potential security issues in chip designs at the sign-off stage.
design for security
Arm gives Helium to low-end Cortex-M core
Arm has added machine-learning extensions and pointer-security instructions to its latest Cortex-M series core.
Codasip pips Arm to commercial CHERI with RISC-V version
Codasip has put support for a set of instruction extensions intended to secure memory into its RISC-V core designs.
Accellera forms CDC working group and takes security standard to IEEE
Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
RISC-V gets verification and security IP additions
Ahead of the RISC-V Summit in San Jose, Imperas Software has issued updates to its ImperasDV verification IP for RISC-V verification and Codasip has launched a secure-processor initiative.
Fault simulator tackles intrusive hacks
Optima DA has turned its high-throughput fault-simulation technology to the checking protections against aggressive, intrusive hacks.
Chiplets may have to prove themselves for secure operation
University of Florida researcher proposes third-party checks on chiplets to demonstrate they are free of trojans.
Glitch detection cores add to Agile portfolio
Agile Analog has moved into the supply of cores for detecting hardware-hacking attempts as well as more conventional data-conversion modules.
Siemens brings chip-design flow to DARPA Toolbox Initiative
Siemens EDA has become the first of the major EDA vendors to join the DARPA Toolbox Initiative.
Connected cars call for safety islands
A Siemens Tessent white papers examines the role of safety islands in advanced automotive systems.