University of Florida researcher proposes third-party checks on chiplets to demonstrate they are free of trojans.
Agile Analog has moved into the supply of cores for detecting hardware-hacking attempts as well as more conventional data-conversion modules.
Siemens EDA has become the first of the major EDA vendors to join the DARPA Toolbox Initiative.
A Siemens Tessent white papers examines the role of safety islands in advanced automotive systems.
Accellera has approved version 1.0 of the SA-EDI standard, intended to provide a consistent way of describing security concerns for IP cores.
Arm aims to introduce a novel security model in its upcoming v9 architecture along with further extensions for AI.
Work presented at IEDM 2020 shows taking advantage of the IC backside for power and ground for the additional area can deliver further benefits for IR drop and security.
The chair of Accellera’s IP security assurance working group expects the draft standard for hardening hardware core to be out by the end of the year.
UltraSoC and Agile Analog have teamed up to build an infrastructure that can help guard against physical attacks on SoCs.
Intel describes active countermeasures for physical attacks at CICC as part of a trend towards more adaptive IoT silicon.
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