Accellera forms CDC working group and takes security standard to IEEE
Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
design for security
RISC-V gets verification and security IP additions
Ahead of the RISC-V Summit in San Jose, Imperas Software has issued updates to its ImperasDV verification IP for RISC-V verification and Codasip has launched a secure-processor initiative.
Fault simulator tackles intrusive hacks
Optima DA has turned its high-throughput fault-simulation technology to the checking protections against aggressive, intrusive hacks.
Chiplets may have to prove themselves for secure operation
University of Florida researcher proposes third-party checks on chiplets to demonstrate they are free of trojans.
Glitch detection cores add to Agile portfolio
Agile Analog has moved into the supply of cores for detecting hardware-hacking attempts as well as more conventional data-conversion modules.
Siemens brings chip-design flow to DARPA Toolbox Initiative
Siemens EDA has become the first of the major EDA vendors to join the DARPA Toolbox Initiative.
Connected cars call for safety islands
A Siemens Tessent white papers examines the role of safety islands in advanced automotive systems.
Accellera approves IP security-documentation standard
Accellera has approved version 1.0 of the SA-EDI standard, intended to provide a consistent way of describing security concerns for IP cores.
Arm looks to explore new realms for security with v9
Arm aims to introduce a novel security model in its upcoming v9 architecture along with further extensions for AI.
Backside metal defends against IR drop and side-channel attacks
Work presented at IEDM 2020 shows taking advantage of the IC backside for power and ground for the additional area can deliver further benefits for IR drop and security.
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