design for security

July 11, 2022

Fault simulator tackles intrusive hacks

Optima DA has turned its high-throughput fault-simulation technology to the checking protections against aggressive, intrusive hacks.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
November 8, 2021

Chiplets may have to prove themselves for secure operation

University of Florida researcher proposes third-party checks on chiplets to demonstrate they are free of trojans.
Article  |  Topics: Blog - EDA, IP, PCB  |  Tags: , , , ,   |  Organizations:
November 2, 2021

Glitch detection cores add to Agile portfolio

Agile Analog has moved into the supply of cores for detecting hardware-hacking attempts as well as more conventional data-conversion modules.
Article  |  Topics: Blog - IP  |  Tags: , ,   |  Organizations:
September 24, 2021

Siemens brings chip-design flow to DARPA Toolbox Initiative

Siemens EDA has become the first of the major EDA vendors to join the DARPA Toolbox Initiative.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations: , , , ,
August 31, 2021

Connected cars call for safety islands

A Siemens Tessent white papers examines the role of safety islands in advanced automotive systems.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , ,   |  Organizations:
July 14, 2021

Accellera approves IP security-documentation standard

Accellera has approved version 1.0 of the SA-EDI standard, intended to provide a consistent way of describing security concerns for IP cores.
Article  |  Topics: Blog - IP  |  Tags: , ,   |  Organizations:
March 31, 2021

Arm looks to explore new realms for security with v9

Arm aims to introduce a novel security model in its upcoming v9 architecture along with further extensions for AI.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , , ,   |  Organizations:
December 18, 2020

Backside metal defends against IR drop and side-channel attacks

Work presented at IEDM 2020 shows taking advantage of the IC backside for power and ground for the additional area can deliver further benefits for IR drop and security.
July 23, 2020

Accellera IP security group expects standard by year end

The chair of Accellera’s IP security assurance working group expects the draft standard for hardening hardware core to be out by the end of the year.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:
April 16, 2020

IP partnership aims to crack down on physical hacks

UltraSoC and Agile Analog have teamed up to build an infrastructure that can help guard against physical attacks on SoCs.
Article  |  Topics: Blog - IP  |  Tags: , , ,   |  Organizations: ,

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