Papers presented at the recent IRPS conference showed the growing importance of lifetime monitoring to the problem of handling components as they age.
DVCon Europe, Accellera’s design and verification conference to be held in Munich in late October, will feature keynotes on the trends toward edge computing and the future of networks.
It's been a long time coming, but silicon photonics is now entering commercial design for networking and grabbing attention in autonomous driving and sensors.
The LightSuite Compiler produces designs based on Python descriptions and certifies them DRC-clean through hooks into the market-leading Calibre DFM suite.
StratoM hardware has 2.5B-gate capacity and can scale to 15B gates. Throughput claimed at 5X faster than earlier Veloce generation.
A licensing deal with GlobalFoundries has provided chipmaker Aquantia with the ability to speed up development of a 100Gbit/s link technology for data centers.
Vendor adds verification support for 25G, 50G and 100G Ethernet through emulator-based virtualization.
HiSilicon claims close collaboration with foundry and EDA tools partners helped speed up plans to tape out the first 16nm finFET-based design through TSMC.
Last week's announcement by Avago that it would buy Broadcom looks to be only partly about bulk. The merger could help drive SIP and 3DIC integration.
A variety of organizations used Embedded World to introduce kits to attract a broader base of developers looking at Internet of Things (IoT) applications.
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