Qualcomm

August 6, 2019

Increased cooperation seen as vital for automotive safety verification

Safety verification calls for increased collaboration across the supply chain, experts say. The challenge is finding ways to make that happen.
April 18, 2019

User2User Silicon Valley is two weeks away

Mentor's technical conference will take place on May 2 at the Santa Clara Marriott and feature more than 45 user and vendor presentations.
November 14, 2018

Case study: Achieving earlier signoff convergence and a ‘shift left’ for P&R at Qualcomm

Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.
Article  |  Topics: Blog - EDA, - GDSII, Verification  |  Tags: , , , , , , ,   |  Organizations: ,
July 27, 2018

Verification engineers embrace emulation for the shift left

In a panel session at June's DAC, Synopsys customers talked about some of the ways they make verification more efficient and bring technologies such as formal, emulation, and simulation together.
July 3, 2018

Fusion improves timing say Synopsys users

Early-access customers talked about their experiences with the Synopsys Fusion-based flow in a panel session at the DAC.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: , , , ,
June 27, 2018

EDA needs to work on the back end, says Qualcomm

It’s the back-end that needs work as system-level considerations begin to dominate design, Qualcomm’s vice president of engineering said at DAC.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,   |  Organizations:
June 25, 2018

Node-variant FinFET tweaks try to improve cost, performance

Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations: , ,
May 4, 2018

7nm process with EUV to feature at VLSI

Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: , , ,
April 9, 2018

DAC keynotes and sessions aim for AI

DAC in June will feature a series of keynotes and technical sessions on machine learning and AI for both target applications and in the design process itself.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations: , , ,
June 21, 2017

Panels see congestion and resistance dominate the leading-edge node battle

Placement-aware synthesis and an array of post-layout recovery steps have helped drive up the clock speed and silicon utilization of a series high-end SoCs on leading-edge processes developed by customers of Synopsys' implementation tools.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: , , , ,

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