Open-source EDA grapples with the incentives issue
As the project that funded OpenRoad draws to a close, experts pondered its wider future at the 59th DAC.
Qualcomm
DVCon Europe explores pitfalls and possibilities of AI for verification
In a panel at this week’s DVCon Europe, experts described a number of issues facing teams looking to incorporate machine learning in logic verification flows and why some of those efforts will not pay off while others succeed.
Nanometer scaling puts focus on power at VLSI in June
Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
GlobalFoundries takes aim at TSMC’s customers in patent action
GlobalFoundries is calling for imports of chips fabbed by TSMC into the US and Germany in multiple actions based on a list of 16 patents.
Increased cooperation seen as vital for automotive safety verification
Safety verification calls for increased collaboration across the supply chain, experts say. The challenge is finding ways to make that happen.
User2User Silicon Valley is two weeks away
Mentor's technical conference will take place on May 2 at the Santa Clara Marriott and feature more than 45 user and vendor presentations.
Case study: Achieving earlier signoff convergence and a ‘shift left’ for P&R at Qualcomm
Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.
Verification engineers embrace emulation for the shift left
In a panel session at June's DAC, Synopsys customers talked about some of the ways they make verification more efficient and bring technologies such as formal, emulation, and simulation together.
Fusion improves timing say Synopsys users
Early-access customers talked about their experiences with the Synopsys Fusion-based flow in a panel session at the DAC.
EDA needs to work on the back end, says Qualcomm
It’s the back-end that needs work as system-level considerations begin to dominate design, Qualcomm’s vice president of engineering said at DAC.
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