In a panel at this week’s DVCon Europe, experts described a number of issues facing teams looking to incorporate machine learning in logic verification flows and why some of those efforts will not pay off while others succeed.
Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
GlobalFoundries is calling for imports of chips fabbed by TSMC into the US and Germany in multiple actions based on a list of 16 patents.
Safety verification calls for increased collaboration across the supply chain, experts say. The challenge is finding ways to make that happen.
Mentor's technical conference will take place on May 2 at the Santa Clara Marriott and feature more than 45 user and vendor presentations.
Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.
In a panel session at June's DAC, Synopsys customers talked about some of the ways they make verification more efficient and bring technologies such as formal, emulation, and simulation together.
Early-access customers talked about their experiences with the Synopsys Fusion-based flow in a panel session at the DAC.
It’s the back-end that needs work as system-level considerations begin to dominate design, Qualcomm’s vice president of engineering said at DAC.
Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.
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