Safety verification calls for increased collaboration across the supply chain, experts say. The challenge is finding ways to make that happen.
Mentor's technical conference will take place on May 2 at the Santa Clara Marriott and feature more than 45 user and vendor presentations.
Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.
In a panel session at June's DAC, Synopsys customers talked about some of the ways they make verification more efficient and bring technologies such as formal, emulation, and simulation together.
Early-access customers talked about their experiences with the Synopsys Fusion-based flow in a panel session at the DAC.
It’s the back-end that needs work as system-level considerations begin to dominate design, Qualcomm’s vice president of engineering said at DAC.
Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.
Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
DAC in June will feature a series of keynotes and technical sessions on machine learning and AI for both target applications and in the design process itself.
Placement-aware synthesis and an array of post-layout recovery steps have helped drive up the clock speed and silicon utilization of a series high-end SoCs on leading-edge processes developed by customers of Synopsys' implementation tools.
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