Nanometer scaling puts focus on power at VLSI in June
Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
dynamic power
Two-day app challenge results in RTL power analyzer
For DAC 2015, Invionics set itself the challenge of developing a custom tool in 48 hours based on votes for ideas provided by visitors to the show.
SRAM IP “halves dynamic power” on 28nm FDSOI
Embedded SRAM IP said to reduce dynamic, static power on FDSOI at cost of extra 10% area
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