TSMC

January 15, 2021

Copper’s future is troubled but it’s likely to stick around

The metal has done sterling service for 20 years but the time is approaching to find a replacement for copper as problems with parasitics continue to build up, work presented at last month’s IEDM shows. But it's not an obvious switch.
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August 25, 2020

TSMC fills in sub-nodes as EUV gains ground

TSMC is using its growing experience with EUV lithography to fill in sub-nodes between its major releases as it prepares to extend finFET technology to the forthcoming N3 process.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , , ,   |  Organizations: ,
July 21, 2020

3D integration technologies will blend says TSMC chief scientist

DTCO and 3D integration will dominate scaling in the coming decade, TSMC chief scientist Philip Wong claimed in his keynote at DAC on Monday
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January 10, 2020

MRAM pushes speed and endurance at IEDM

IEDM late last year showed how MRAM is being prepared for both FD-SOI and advanced finFET nodes.
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October 29, 2019

Foundries call off patent war

GlobalFoundries and TSMC have called off their legal battle with a wide-ranging patent cross-licensing deal.
Article  |  Topics: Blog - EDA, IP  |  Tags: ,   |  Organizations: ,
October 14, 2019

Integration forms highlights of upcoming IEDM

Different forms of heterogeneous integration take center stage at the IEEE International Electron Device Meeting (IEDM) in December this year.
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August 27, 2019

GlobalFoundries takes aim at TSMC’s customers in patent action

GlobalFoundries is calling for imports of chips fabbed by TSMC into the US and Germany in multiple actions based on a list of 16 patents.
Article  |  Topics: Blog - IP  |  Tags: , , , ,   |  Organizations: , , ,
June 6, 2019

Calibre scales to 4000 nodes for faster sign off in the cloud

AMD used Calibre with optimisations implemented for cloud support to slash runtimes on high-end server processor designs.
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April 22, 2019

Machine learning and chiplets headline VLSI Symposia

Large-scale MCMs and novel device architectures bookend the papers on machine learning at VLSI Symposia in an event that will also cover chiplet integration and other topics.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations: , ,
April 18, 2019

User2User Silicon Valley is two weeks away

Mentor's technical conference will take place on May 2 at the Santa Clara Marriott and feature more than 45 user and vendor presentations.

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