RealIntent

There's still plenty of time to build a busy and profitable agenda for a visit to ES Design West and SEMICON West in San Francisco next week.

ES Design West was created to reflect integration, even elision of tasks across the semiconductor supply chain. Here's how the program reflects the trend.

Real Intent's move into post-synthesis CDC debug leads its DAC 2018 activities, with technical papers on its new Verix PhyCDC tool also now online for those who cannot make it.

Meridian Constraints update seeks to extend existing capabilities and address a gap not covered by other functional verification tools.

The functional verification specialist will discuss the latest updates to Ascent and Meridian - and offer top quality espresso at this year's conference.

Verification specialist's DVCon activities are headlined by a panel on emulation and static verification.

Real Intent has lined up a mixture of technology and speed tests for its presence on Booth #1422 at the Design Automation Conference this year.

Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.

Ascent Lint adds checks for DO-254, tighter integration with HDL Coder, more SystemVerilog support and new VHDL and Verilog rules in March update.

Major overhaul of clock domain crossing suite adds configurable debugger, boosts performance by 30% and cuts memory 40% for 'giga-scale' designs.