RealIntent

July 2, 2019

The road to ES Design West: Location, location, location

There's still plenty of time to build a busy and profitable agenda for a visit to ES Design West and SEMICON West in San Francisco next week.
June 20, 2019

The road to ES Design West: Systems

ES Design West was created to reflect integration, even elision of tasks across the semiconductor supply chain. Here's how the program reflects the trend.
June 21, 2018

DAC 2018 preview: Real Intent

Real Intent's move into post-synthesis CDC debug leads its DAC 2018 activities, with technical papers on its new Verix PhyCDC tool also now online for those who cannot make it.
Article  |  Topics: Conferences, Blog - EDA, - Verification  |  Tags: , , ,   |  Organizations:
May 26, 2016

Real Intent extends Meridian Constraints for untimed paths

Meridian Constraints update seeks to extend existing capabilities and address a gap not covered by other functional verification tools.
May 25, 2016

DAC 2016 preview: Real Intent

The functional verification specialist will discuss the latest updates to Ascent and Meridian - and offer top quality espresso at this year's conference.
Article  |  Topics: Conferences, RTL, Verification  |  Tags: , ,   |  Organizations:
February 22, 2016

DVCon United States 2016 preview: Real Intent

Verification specialist's DVCon activities are headlined by a panel on emulation and static verification.
June 5, 2015

DAC2015: Real Intent at the Design Automation Conference

Real Intent has lined up a mixture of technology and speed tests for its presence on Booth #1422 at the Design Automation Conference this year.
Article  |  Topics: Blog - EDA  |  Tags:   |  Organizations:
May 21, 2015

Real Intent tackles CDC at the physical level

Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.
February 25, 2015

Real Intent updates linter for aviation, Mathworks and SystemVerilog

Ascent Lint adds checks for DO-254, tighter integration with HDL Coder, more SystemVerilog support and new VHDL and Verilog rules in March update.
September 30, 2014

Real Intent’s Meridian CDC flexes hierarchical muscle, adds flexible debug

Major overhaul of clock domain crossing suite adds configurable debugger, boosts performance by 30% and cuts memory 40% for 'giga-scale' designs.
Article  |  Topics: Verification  |  Tags: , ,   |  Organizations:

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