RealIntent

Real Intent has developed a tool for identifying potential security issues in chip designs at the sign-off stage.

Real Intent has developed a tool to check design and the potential for circuits to glitch.

Real Intent has upgraded its Meridian CDC clock-domain crossing sign-off tool, with support for multimode-aware dynamic models.

Real Intent has extended the fault coverage of its Meridian DFT static sign-off tool with improvements to the reporting of issues and the ability to track down root causes.

Real Intent has launched a DFT tool intended to relax the bottlenecks that occur as an SoC project moves into its final phase ahead of tapeout.

The parser specialist has built a loyal fanbase across the electronics system design infrastructure with users now lining up to mark its 20th birthday.

There's still plenty of time to build a busy and profitable agenda for a visit to ES Design West and SEMICON West in San Francisco next week.

ES Design West was created to reflect integration, even elision of tasks across the semiconductor supply chain. Here's how the program reflects the trend.

Real Intent's move into post-synthesis CDC debug leads its DAC 2018 activities, with technical papers on its new Verix PhyCDC tool also now online for those who cannot make it.

Meridian Constraints update seeks to extend existing capabilities and address a gap not covered by other functional verification tools.