A new white paper offers useful tips and techniques for PDN analysis and performance optimization in designs such as those using DDR4.
At December's Design Automation Conference, AMD senior vice president Sam Naffziger provided more insights into the chipmaker’s use of chiplet-based design and manufacture.
FHE use-cases are evolving and the NextFlex consortium is looking to smooth their path with a strategy, PDKs and reference modules.
University of Florida researcher proposes third-party checks on chiplets to demonstrate they are free of trojans.
Arm’s SystemReady program has revealed a number of the subtleties involved when trying to maintain software compatibility with operating systems without moving to the straightjacket of platforms like those used for the x86-based PC.
What companies do internally to digitalize matters, but so does using the concept to optimize their supply chain with partners.
Cadence has built a unified database to support a group of tools to support the planning and implementation of 3DIC designs.
Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.
A de facto standard for exchanging thermal information about designs has become JEDEC standard JEP181.
Siemens has introduced a cloud-based DFM tool intended to bridge the gap between the electronics design and manufacturing.
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