power grid


June 16, 2020

Transistor stacks piled high at VLSI

As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , , , , ,   |  Organizations: ,
December 7, 2016

Overcoming electromigration analysis limitations for larger on-die power grids

Award-winning paper describes new strategy offering both greater speed and accuracy.
Article  |  Topics: Blog Topics  |  Tags: , , ,   |  Organizations: , ,
October 3, 2014

ARM tools take aim at finFET layout, timing issues

ARM has launched a pair of tools designed to improve the density and performance of finFET designs that use the company's physical libraries.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , , ,   |  Organizations:
November 12, 2013

Cadence ties IR drop into static timing analysis

Cadence Design Systems uses parallelism in its Voltus tool to provide faster IR drop analysis and bridge static timing and IC-level power-integrity analysis.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors