Mentor's technical conference will take place on May 2 at the Santa Clara Marriott and feature more than 45 user and vendor presentations.
Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.
Power analysis specialist will showcase the 2.0 edition of its PowerBaum analysis and modeling suite at DAC.
Taiwanese ASIC specialist Alchip discusses use of Mentor PowerPro for low power on 16nm 24x24 array HPC chip in detail
Synopsys' line-up at next week's ARM TechCon includes joint presentations with Huawei and Nvidia.
Mentor will present seven papers during the ARMTech Con and a dedicated session, and exhibit at Booth #606.
Start-up Baum is co-located with Verific at DAC 2017 and will demonstrate its soon-to-launch power analysis and modeling software.
Learn how to pre-empt timing and congestion issues that could arise after synthesis by using 'PlaceFirst' technology within Oasys-RTL.
The functional verification specialist will discuss the latest updates to Ascent and Meridian - and offer top quality espresso at this year's conference.
An overview of the vendor's busy DAC program from panels to technical sessions to a one-to-one with Wally Rhines.
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