RTL

October 4, 2019

Master the design and verification of next gen transport: Part Three – functional safety

The third part of this series takes the original CNN demonstrator through a full ISO 26262 type functional safety workflow
October 2, 2019

Master the design and verification of next gen transport: Part Two – high-level synthesis

An object classification demonstrator shows how high-level synthesis (HLS) can speed the delivery and exploration of automotive design.
July 5, 2019
ES Design West logo

The road to ES Design West: Design Pavilion

ES Design West aims to help integrate the supply chain but also has plenty of engineering content aimed at low power, security, embedded and more.
April 18, 2019

User2User Silicon Valley is two weeks away

Mentor's technical conference will take place on May 2 at the Santa Clara Marriott and feature more than 45 user and vendor presentations.
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February 26, 2019

A hardware-centric approach to checking HLS code before synthesis

Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.
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June 19, 2018

DAC 2018 preview: Baum

Power analysis specialist will showcase the 2.0 edition of its PowerBaum analysis and modeling suite at DAC.
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May 24, 2018

Case study demonstrates 59% extra power savings for HPC

Taiwanese ASIC specialist Alchip discusses use of Mentor PowerPro for low power on 16nm 24x24 array HPC chip in detail
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October 17, 2017

Arm TechCon 2017 preview: Synopsys

Synopsys' line-up at next week's ARM TechCon includes joint presentations with Huawei and Nvidia.
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October 17, 2017

Arm TechCon 2017 preview: Mentor

Mentor will present seven papers during the ARMTech Con and a dedicated session, and exhibit at Booth #606.
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June 16, 2017

DAC 2017 preview: Baum

Start-up Baum is co-located with Verific at DAC 2017 and will demonstrate its soon-to-launch power analysis and modeling software.
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