December 21, 2020
Work by the University of Toronto and Arm presented at IEDM indicates plasmonics could be a viable contender for high-speed chip-chip communications.
December 18, 2020
Work presented at IEDM 2020 shows taking advantage of the IC backside for power and ground for the additional area can deliver further benefits for IR drop and security.
December 15, 2020
Imec's senior vice president of CMOS outlined future directions for the technology over the coming decade.
December 4, 2020
Study may point to new challenges in more bidirectional AMS implementations on SoC-class designs, though formal and emulation help keep respin count in check.
November 9, 2020
This year's IEDM will feature papers that exploit stacked nanoribbons to reduce CMOS footprint, graphene interconnects that support easier integration, and the variability prospects of 2D semiconductors.
July 21, 2020
DTCO and 3D integration will dominate scaling in the coming decade, TSMC chief scientist Philip Wong claimed in his keynote at DAC on Monday
July 13, 2020
Heterogeneous integration has the potential to overcome the yield and cost challenges presented by the growing headwinds associated with process scaling. But it may take a dramatic rethink in design approaches.
June 16, 2020
As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.
May 26, 2020
Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
December 18, 2019
Imec, TNO, and Cartamundi have developed a low-cost way of letting tags communicate with embedded devices wirelessly by using a capacitive touchscreen.