Verification

October 26, 2020
Featured image - cel-name conflict resolution

Resolving IP cell-name conflicts peacefully

One roadblock to the integration of IP from multiple vendors into an SoC is the likelihood of finding duplicate cell names in the merged design. Carefully considered renaming strategies can fix the problem without causing design database bloat.
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September 25, 2020
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

Extract benefit from the automated refactoring of VHDL code

VHDL has come a long way in terms of complexity. An integrated development environment helps you deliver better and more compliant code quickly.
September 21, 2020
filler cells featim sep20

P&R filler cell insertion slowing you down? Replace it

A physical verification-ready flow can speed project delivery by making your use of filler cells more efficient.
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September 7, 2020
Ashish Darbari is CEO of formal verification consultancy and training provider Axiomise.

Everything you ever wanted to know about RISC-V architectural formal verification

But you were NOT afraid to ask.... It's time for some answers.
August 25, 2020
Hend Wagieh is the senior product manager for Calibre circuit verification at Mentor, a Siemens Business. Her responsibilities include defining the product roadmap, business strategies, and associated new use models needed to grow the product line and increase market competitiveness for the Calibre nmLVS platform. Hend holds a degree in Electronics and Communication Engineering from Ain Shams University in Cairo, Egypt.

Creating a new paradigm for circuit verification

How Calibre is evolving to address the challenges of LVS verification in early-stage design.
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August 14, 2020
John Ferguson is the product management director for Calibre DRC applications at Mentor, a Siemens BusinessHe holds a B.Sc. degree in Physics from McGill University, an M.Sc. in Applied Physics from the University of Massachusetts, and a Ph.D. in Electrical Engineering from the Oregon Graduate Institute of Science and Technology.

EDA innovation is the foundation of progress

For physical verification and beyond, each process node requires new thinking, new tools and greater performance.
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August 12, 2020
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

How IDEs enable the ‘shift left’ for VHDL

Learn how an IDE offers on-the-fly, auto-correct and informed analysis of VHDL code to speed project quality and delivery.
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June 9, 2020
place and route in design automated hotspot fixing

How to achieve fast, automated, sign-off verification of DFM hotspot fixes in P&R

A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.
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June 4, 2020
UVM - Universal Verification Methodology

UVM coding guidelines offer clarity in a complex world

These 13 suggestions toward best practice address some of the most persistent challenges with the Universal Verification Methodology.
June 2, 2020
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

VHDL users also deserve efficient design and verification

More commonly associated with SystemVerilog, IDEs can also greatly help users of the popular HDL for FPGA, mil/aero and other designs.
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