One roadblock to the integration of IP from multiple vendors into an SoC is the likelihood of finding duplicate cell names in the merged design. Carefully considered renaming strategies can fix the problem without causing design database bloat.
VHDL has come a long way in terms of complexity. An integrated development environment helps you deliver better and more compliant code quickly.
A physical verification-ready flow can speed project delivery by making your use of filler cells more efficient.
But you were NOT afraid to ask.... It's time for some answers.
How Calibre is evolving to address the challenges of LVS verification in early-stage design.
For physical verification and beyond, each process node requires new thinking, new tools and greater performance.
Learn how an IDE offers on-the-fly, auto-correct and informed analysis of VHDL code to speed project quality and delivery.
A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.
These 13 suggestions toward best practice address some of the most persistent challenges with the Universal Verification Methodology.
More commonly associated with SystemVerilog, IDEs can also greatly help users of the popular HDL for FPGA, mil/aero and other designs.
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