More optimistic about the semiconductor industries prospects than for some time, Siemens Joe Sawicki identified key EDA challenges at DAC.
Automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis. This tutorial, first presented at DVCon Europe explores how these formal techniques can be deployed and provides real-world examples.
Learn how Calibre 3D enables circuit and layout verification multi-die assemblies so that heterogeneous die processes can co-exist without significant impact to the deck.
Pre- and post-processing EDA techniques help streamline design rule checks and delivery efficient waivers to speed design and debug.
PIM memory boosts efficiency by operating on data without moving it to the CPU but realizing this type of novel technology posed power integration and planning challenges.
Innovation is extending the technique's power across areas such as context-aware layout, accounting for multi-patterning and implementing fill.
SiP promises advances in transmission speeds, bandwidth, accuracy and low power but verification requires careful evolution of existing tools.
Learn how to bring together your NLDM and CCS models to reach timing closure faster with Solido Analytics.
Overcome problems created by mismatches between library exchange format (LEF) and GDS or OASIS representations to avoid design delays.
Using on-demand rule checks during place-and-route boosts efficiency and design quality.
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