Research Groups

June 20, 2014

14nm FD-SOI pushes strain and body bias for power savings

At the VLSI Technology Symposium a team led by STMicroelectronics described the techniques used for the upcoming 14nm FD-SOI to boost speed and density over the 28nm version.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , ,   |  Organizations: , ,
April 7, 2014

Latest ITRS underlines slowdown in interconnect and IC scaling

The 2013 edition of the International Technology Roadmap for Semiconductors has been published. The latest set of tables underlines the slowdown in some aspects of scaling, particularly when it comes to metal interconnect.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: , ,
April 4, 2014

Silicon suppliers home in on energy-harvesting sensor nodes

Power converters are arriving on the market with the aim of simplifying the job of building energy-harvesting systems for wireless sensor nodes and the Internet of Things.
March 26, 2014

Even EUV faces a 1D future, says IMEC

IMEC's Rudy Lauwereins explained at DATE 2014 how 1D routing for self-aligned multiple patterning is likely to be inevitable even if EUV makes it into production fabs.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
March 25, 2014

The 1ms difference for embedded systems

What's in a millisecond? The difference between today's embedded systems and tomorrow's, Professor Gerhard Fettweis of TU of Dresden said at DATE 2014.
Article  |  Topics: Blog - Embedded  |  Tags: , , , ,   |  Organizations:
November 20, 2013

FinFETs’ III-V future promises sub-7nm, RF and opto CMOS

FinFETs for 7nm and below processes will be able to integrate high-mobility III-V materials despite being built on silicon processes, thanks to recent work by imec.
Article  |  Topics: Design to Silicon, Blog - EDA  |  Tags: ,   |  Organizations:
October 4, 2013

Design kit for 10nm FD-SOI due out next year

Research group CEA-Leti expects to have design kits ready for a 10nm FD-SOI process in June 2014
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
June 3, 2013

CMOS “good for another century,” says father of finFET

CMOS approaches are likely to underpin electronics for the next century, according to Chenming Hu, father of the finFET
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
April 10, 2013

3D-IC cooling ascends the agenda

US defense research agency DARPA sets targets for cooling overall systems and hot spots in stacked silicon, and backs joint research from Rockwell-Collins and Georgia Tech.
Article  |  Topics: Design to Silicon, Blog - EDA  |  Tags: ,   |  Organizations: , ,
March 27, 2013

Intel and ST stake claims to foundry low power designs

With both now more dependent on foundry business for their finFET (trigate) and FDSOI offerings, DATE was a chance to push their innovations in low power.

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