ES Design West aims to help integrate the supply chain but also has plenty of engineering content aimed at low power, security, embedded and more.
A new paper describes an alternative to increasingly inefficient manual ESD verification that reduces risks of respins and missed delivery deadlines.
Mentor takes the wraps off new machine learning fueled features in its HLS and physical design families ahead of DAC 2019.
Mentor's technical conference will take place on May 2 at the Santa Clara Marriott and feature more than 45 user and vendor presentations.
Synopsys is taking IC design on TSMC processes into the cloud with the launch of the Synopsys Cloud Solution, which will run on platforms from Synopsys, Amazon Web Services (AWS) or Microsoft Azure.
The LightSuite Compiler produces designs based on Python descriptions and certifies them DRC-clean through hooks into the market-leading Calibre DFM suite.
Collaboration on DTCO offers IBM a better way to evaluate combinations of transistor architectures, materials and other process technology innovations using design metrics, before real wafers become available for physical experimentation.
LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.
DATE highlights for Mentor include a 90-minute workshop on achieving functional safety for autonomous driving.
Innovation and advances in EUV and OPC lead Mentor's offerings at SPIE in San Jose later this month.
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