Putting chiplet design on the ‘smart path’
The flat nature of traditional IC packaging design struggles to cope with the chiplet era. Homogeneous disaggregation offers an alternative.
Next Generation Design
Benchmarking the maturity of AI in EDA
Solido discusses how it has leveraged AI for SPICE level efficiency and the benchmarks it has used.
ETRI builds flow for AI chiplets
South Korea's leading research institute has built a reusable flow for lower power petaflops-performance AI.
Catch up with the state-of-the-art in ‘shift left’
Just how much of the flow has already has 'shift left' benefit and what is fueling further progress.
Chipletz pushes packaging design for AI, HPC and immersive use-cases
The Austin-based start-up used Siemens EDA software to deploy a cutting-edge Smart Substrate based on advanced packaging technology.
How digital twin evaluations optimize STCO-based design
System Technology Co-optimization raises various SI, PI, thermal, mechanical and warp risks due to its use of advanced packaging. Early-stage prototyping mitigates them.
Flexible hybrid electronics: Making an emerging tech happen with PDKs and reference designs
FHE use-cases are evolving and the NextFlex consortium is looking to smooth their path with a strategy, PDKs and reference modules.
Siemens extends Solido’s reach into IP validation with Fractal
Latest acquisition adds technologies to mitigate rising verification time and cost for third-party IP.
Getting a RISC-V embedded toolchain in place
A new white paper reviews the history of the open-source platform and provides guidance on best practice development for embedded.
RISC-V in nearly a quarter of designs (Wilson Functional Verification 2020 – Part One)
Use of the open-source RISC-V processor was tracked for the first time by the biennial study, finding notably high take-up.
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