That said, the fundamentals of SoC design are still at the heart of the event. Below we look at how that is reflected in its six Design Pavilion sessions. First, though, here is what some of the exhibitors are expecting from the event.
“We provide our customers best in class verification software and are looking forward to showcasing the Visual Verification Suite at ES Design West,” says Ellis Smith, Chairman and CEO of Blue Pearl Software.
Dave Kelf, Chief Marketing Officer for Breker Verification Systems, identifies another of the conference’s objectives: Positioning the latest developments in EDA alongside those elsewhere across the industry.
“ES Design West’s strong and authoritative system-centric program offers a new perspective for the electronic design ecosystem,” he says. “This is especially valuable as the Portable Stimulus Standard from Accellera becomes central to engineering groups with complex design verification flows.”
As noted, dedicated EDA and IP issues will be highlighted in six Design Pavilion sessions alongside the exhibitors. All have agendas that aim to deliver practical design advice ranging across specific techniques to broader methodologies. They also consider what is available through alliances and platform-specific ecosystems. And engineers who have done the job will be sharing their experiences.
We have previously looked at three topics that fill the Design Pavilion slots. The Silicon Design in the Cloud session (Wednesday, July 10) is covered in our preview on Cloud-based implementations. Machine Learning, AI and EDA (Wednesday, July 10) features in the AI preview. Finally, Advanced Applications (Thursday, July 11) is part of the Systems preview.
Here we describe what you can expect from the remaining three sessions: More than Moore, Design for Low Energy and Security. You can review them all, or scroll down to the one most appropriate to your needs.
More than Moore at ES Design West
The More than Moore session (Tuesday, July 9) features speakers from Arm, DARPA, Silvaco and Synopsys.
Chan-Su Yun, senior R&D manager at Synopsys, will describe strategies that use physics-based modeling in a single chip-to-package DFM flow for power electronics (10.35am).
Andreas Olaffson, program manager with the DoD DARPA research agency, will consider IP reuse, particularly in the context of complex (and therefore more expensive) designs for fabrication in low volumes – a particular issue for defense applications. He will do this via an update on the agency’s CHIPS program (Common Heterogeneous Integration and Intellectual Property) (11.05am).
Babek Taheri, CTO and Executive Vice President of Products for Silvaco, will review the challenges and solutions for design-technology co-optimization (DTCO) using TCAD and design IP for next generation SoCs (11.35am).
Rupal Gandhi, Technical Marketing Manager with Arm, will outline best design practices for power optimization in the context of her company’s latest Artisan physical IP and newer implementation possibilities using the Cortex CPU (12.05pm).
Designing for Low Energy at ES Design West
The Design Pavilion session on Designing for Low Energy (Tuesday, July 9) comprises presentations from Eta Compute, Minima Processor, NXP, Rambus and Synopsys.
Helena Handschuh, Security Technologies Fellow at Rambus will consider the low-power issues that face embedded designs, primarily for mobile applications ranging from traditional communications to the Internet of Things (1.35pm).
David Baker, Chief Architect for Eta Compute, will describe what his company has achieved in embedded processing with the use of dynamic voltage and frequency scaling (DVFS). He will refer specifically to its work on the ECM3531 SoC that contains a self-timed (DIAL3) ARM Cortex-M3 (2.05pm).
Nihaar Mahatme, Technology Strategy Lead for the Microcontrollers Business Line at NXP will address the important trend in greater edge processing for IoT and other devices. He will describe techniques to achieve a balance of performance and power within clustered and distributed systems (2.35pm).
Lauri Koskinen, CTO and Co-founder of Minima Processor will look at what can be achieved in ultra-low-power design using dynamic margining to enable ultra-wide DVFS. Dynamic margining is a hardware-software optimization based on netlist-level logic (3.05pm).
Godwin Maben, Synopsys Scientist, will offer a higher level view that looks at low-power strategies for ASIC design that bring together EDA capabilities in functional verification, logical/physical implementation and signoff within a single methodology (3.35pm).
Security at ES Design West
The Design Pavilion session on Security (Thursday, July 11) features presentations from Arm, Intel and Secure-IC as well as a panel discussion featuring Ansys and Synopsys.
Mike Eftimakis, Director of Business Innovation Strategy at Arm, will highlight ongoing work on the cross-industry Platform Security Architecture (PSA) initiative. The first PSA-certified products have been announced under the four-phase scheme that aims to provide a multi-level security framework from analysis to certification (10.35am).
Norman Chang, Chief Technologist for the Semiconductor Business Unit at Ansys, and Mike Borza Member of the Technical Staff at Synopsys will join editor Ed Sperling for a discussion of ‘The Threat Level On Hardware’ (11.05am).
Sylvain Guilley, CTO of Secure-IC, will describe the multi-faceted layering of security technologies within use cases that deploy his company’s Securyzr technology. Layers considered will include client authentication, access rights management and event logging (11.35am).
Richard Kerslake, IoT Program Director in the Internet of Things Group at Intel will talk about overcoming the vulnerabilities in onboarding a device to a platform or the cloud through automation rather than the still widespread use of manual setup (12.05pm).