Imec has a version of its imec.netzero virtual fab tool accessible to the general public with the aim of showing the environmental impact of IC manufacturing.
Backside power delivery could lead to improvements in chip density and more straightforward place-and-route phases according to work presented at this year’s VLSI Symposium.
AT&S and Imec partnered to develop a way of putting low-loss waveguides into conventional PCBs to support D-band automotive radar and 6G modules.
Adding an MOL layer that takes advantage of a self-aligned pitch-splitting technique and a rotated layout could cut standard-cell height to 4T.
Imec has developed a high-endurance ferroelectric capacitor that could form the basis of storag-class embedded and standalone memories.
At IEDM, TSMC is at the top of several papers that examine how 2D materials might be put into action as successors to silicon, alongside work from a variety of institutions on power integration and thermal management.
VLSI Symposium 2022 will show the rapid development taking place in oxide-based replacements for traditional DRAM cells as well as the emerging area of memory-based low-power machine learning.
Three highlighted papers at IEDM, taking place in December, show the different approaches to the use of the vertical dimension to cut energy use and improve density.
Imec showed at VLSI Symposia a process flow that can cut the gap between complementary transistors to less than 20nm.
The upcoming VLSI Symposia will feature a number of papers that show the ways in which novel approaches are going to be needed to continue scaling.
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