Heterogeneous integration has the potential to overcome the yield and cost challenges presented by the growing headwinds associated with process scaling. But it may take a dramatic rethink in design approaches.
As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.
Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
Imec, TNO, and Cartamundi have developed a low-cost way of letting tags communicate with embedded devices wirelessly by using a capacitive touchscreen.
Different forms of heterogeneous integration take center stage at the IEEE International Electron Device Meeting (IEDM) in December this year.
There's still plenty of time to build a busy and profitable agenda for a visit to ES Design West and SEMICON West in San Francisco next week.
Embedded magnetic RAM is emerging as a contender for on-chip memory not just from a density standpoint but from that of power.
CMOS moving to 3nm and DRAM going beyond 20nm scaling are two of the late papers at the upcoming IEDM and part of a larger examination of semiconductor trends.
Imec proposes using stacked CMOS transistors and buried power rails to improve density for the 3nm process node.
Imec will at this week’s VLSI Symposia describe how it fabricated a form of magnetic memory suitable for use as a non-volatile cache onto 300mm wafers using CMOS-compatible processes.
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