junction-less transistor

June 16, 2020

Transistor stacks piled high at VLSI

As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , , , , ,   |  Organizations: ,
January 30, 2013

Mentor updates HyperLynx for faster boards, more rules checking

Mentor's HyperLynx gets speed and accuracy enhancements, as well as more embedded help, to speed up fast board design
Article  |  Topics: Blog - PCB  |  Tags: , , ,   |  Organizations:
October 5, 2012

IEF: Process kits for processes that don’t yet exist

Designers should plan ahead for future process changes as conventional silicon CMOS runs out of steam, IMEC's Rudy Lauwereins told delegates at the International Electronics Forum in Bratislava this week.
Article  |  Topics: Conferences, Design to Silicon, Blog - EDA  |  Tags: , , ,   |  Organizations:


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