May 23, 2018
Imec and Unisantis Electronics have developed a process flow based on a vertical transistor with a gate on all sides they claim will lead to denser memories on a 5nm node.
May 11, 2018
The circuits sessions at mid-June's VLSI Symposia in Honolulu feature a number of papers that improve the performance of scaled mixed-signal processes.
May 4, 2018
Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
April 9, 2018
DAC in June will feature a series of keynotes and technical sessions on machine learning and AI for both target applications and in the design process itself.
April 5, 2018
PDK enables photonics prototyping on MPW runs and compatibility with volume production at STMicroelectronics at Crolles.
February 28, 2018
Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
December 6, 2017
Two leading European research institutes presented their work on the feasibility and cost-effectiveness of monolithic 3D integration at this year's IEDM.
October 18, 2017
Intel and GlobalFoundries will talk about their post-14nm finFET-based processes at December's IEDM.
May 2, 2017
DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.
February 13, 2017
The major West Coast technical conference for lithography is just two weeks away and offers a packed agenda.