Research Groups

April 7, 2016

SNUG 2016: Intel, TSMC, GloFo back post-finFET research at UC Berkeley

But project lead Chenming Hu, 'finFET's father', has also highlighted important changes in the funding landscape for university research.
March 11, 2016

GSA on how to reinvigorate silicon business models

Open-source hardware, in-field configurability, and a hardware-plus-services approach could protect margins as the IoT hammers down costs, says GSA report.
December 15, 2015

GaN power makes progress at IEDM 2015

Researchers describe at IEDM 2015 how they are making gallium nitride fit into a wider range of power-handling applications and may even result in mass-market vertical transistors.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , ,   |  Organizations: ,
December 7, 2015

Asymmetric variability issues could impact 7nm processes

Simulation shows 7nm process will need tighter variability control than expected, and possibly accommodation for asymmetric variability
Article  |  Topics: Conferences, Design to Silicon  |  Tags: , , ,   |  Organizations: , ,
November 12, 2015

DVCon Europe: UVM-SystemC backers ready first draft

But the bridge standard's European backers still need greater support from the big EDA vendors.
October 9, 2015

IMEC 5nm test chip to explore EUV and SAQP litho options

IMEC and Cadence have taped out a test chip intended to explore key lithography and metal-interconnect issues that will face users of the forthcoming 5nm process node.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
July 9, 2015

IBM and friends at 7nm: breakthrough or science project?

IBM, GlobalFoundries, Samsung and SUNY deserve kudos for manufacturing the first 7nm chip but the NREs involved still look frightening.
June 18, 2015

The road to 7nm sees patterning multiply

Is the industry ready to go beyond 10nm when it comes to lithography? Lithography researcher Professor David Pan sees design and process co-operation as the key approach.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: , ,
June 8, 2015

CEA-Leti adds partners to FD-SOI low-power design centre

Silicon Impulse program adds partners to ease industrialisation of ultra-low power IC designs based on FD-SOI processes
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations: , ,
May 11, 2015

VLSI Symposia delve into future process choices

Intel 14nm finFET SoC process is among the highlights of the 2015 VLSI Symposia alongside research that looks at the integration of III-V and 2D materials for future processes.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , ,   |  Organizations: , , ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors