But project lead Chenming Hu, 'finFET's father', has also highlighted important changes in the funding landscape for university research.
Open-source hardware, in-field configurability, and a hardware-plus-services approach could protect margins as the IoT hammers down costs, says GSA report.
Researchers describe at IEDM 2015 how they are making gallium nitride fit into a wider range of power-handling applications and may even result in mass-market vertical transistors.
Simulation shows 7nm process will need tighter variability control than expected, and possibly accommodation for asymmetric variability
But the bridge standard's European backers still need greater support from the big EDA vendors.
IMEC and Cadence have taped out a test chip intended to explore key lithography and metal-interconnect issues that will face users of the forthcoming 5nm process node.
IBM, GlobalFoundries, Samsung and SUNY deserve kudos for manufacturing the first 7nm chip but the NREs involved still look frightening.
Is the industry ready to go beyond 10nm when it comes to lithography? Lithography researcher Professor David Pan sees design and process co-operation as the key approach.
Silicon Impulse program adds partners to ease industrialisation of ultra-low power IC designs based on FD-SOI processes
Intel 14nm finFET SoC process is among the highlights of the 2015 VLSI Symposia alongside research that looks at the integration of III-V and 2D materials for future processes.
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