This year's IEDM will feature papers that exploit stacked nanoribbons to reduce CMOS footprint, graphene interconnects that support easier integration, and the variability prospects of 2D semiconductors.
DTCO and 3D integration will dominate scaling in the coming decade, TSMC chief scientist Philip Wong claimed in his keynote at DAC on Monday
Heterogeneous integration has the potential to overcome the yield and cost challenges presented by the growing headwinds associated with process scaling. But it may take a dramatic rethink in design approaches.
As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.
Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
Imec, TNO, and Cartamundi have developed a low-cost way of letting tags communicate with embedded devices wirelessly by using a capacitive touchscreen.
Different forms of heterogeneous integration take center stage at the IEEE International Electron Device Meeting (IEDM) in December this year.
ES Design West aims to help integrate the supply chain but also has plenty of engineering content aimed at low power, security, embedded and more.
The US Quantum Economic Development Consortium is looking to stimulate a supply chain and technology infrastructure for quantum computing, with more about its efforts due to come out in the next few days.
There's still plenty of time to build a busy and profitable agenda for a visit to ES Design West and SEMICON West in San Francisco next week.
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