monolithic 3DIC

The upcoming VLSI Symposium will examine progress in using backside contacts and 3D structures to improve density and speed as well as continuing improvements to finFET processes.

At IEDM, CEA-Leti described a process that avoids the thermal problems of implementing CMOS transistors in the metal stack using monolithic integration.

Vertical integration is one of the major focus areas at the upcoming IEDM conference, both in terms of transistors and the multiple channels that will go into them.

Western Digital's head of technology set out at the recent VLSI Symposium the ways in which flash makers can scale without costs accelerating.

Recognizing the 75th anniversary of the transistor in December, the 68th IEDM has taken on the theme of looking at “transformative devices to address global challenges”.

Three highlighted papers at IEDM, taking place in December, show the different approaches to the use of the vertical dimension to cut energy use and improve density.

Samsung described at VLSI Symposia how it has used two further forms of stacking to increase flash capacity.

IEDM has issued a call for papers for what the organizers expect to be an in-person event in December.

At IEDM this year, Macronix showed how a 3D architecture may bring back NOR flash, which stopped scaling a decade ago.

Imec's senior vice president of CMOS outlined future directions for the technology over the coming decade.