monolithic 3DIC

June 16, 2021

Samsung moves further into 3D for denser flash

Samsung described at VLSI Symposia how it has used two further forms of stacking to increase flash capacity.
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June 4, 2021

IEDM looks for papers across 2D devices to 3DICs

IEDM has issued a call for papers for what the organizers expect to be an in-person event in December.
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December 17, 2020

Macronix proposes 3D to breathe life back into NOR flash

At IEDM this year, Macronix showed how a 3D architecture may bring back NOR flash, which stopped scaling a decade ago.
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December 15, 2020

Chipmaking’s new environment presented at IEDM

Imec's senior vice president of CMOS outlined future directions for the technology over the coming decade.
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July 21, 2020

3D integration technologies will blend says TSMC chief scientist

DTCO and 3D integration will dominate scaling in the coming decade, TSMC chief scientist Philip Wong claimed in his keynote at DAC on Monday
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June 16, 2020

Transistor stacks piled high at VLSI

As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.
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October 14, 2019

Integration forms highlights of upcoming IEDM

Different forms of heterogeneous integration take center stage at the IEEE International Electron Device Meeting (IEDM) in December this year.
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December 5, 2018

Leti takes the heat off monolithic 3D

CEA-Leti claimed at IEDM to have achieved major steps in bringing monolithic 3D integration closer to production readiness.
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June 22, 2018

Imec stacks transistors for denser 3nm option

Imec proposes using stacked CMOS transistors and buried power rails to improve density for the 3nm process node.
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December 6, 2017

European teams explore 3D integration tradeoffs

Two leading European research institutes presented their work on the feasibility and cost-effectiveness of monolithic 3D integration at this year's IEDM.
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