Verification

March 26, 2019

UVM Cookbook released in new edition

Popular Verification Academy manual revamped and updated to bring it more closely in line with IEEE 1800.2 UVM and reflect the increasing use of emulation.
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February 26, 2019

A hardware-centric approach to checking HLS code before synthesis

Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.
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February 22, 2019

DVCon USA 2019 preview: OneSpin

OneSpin will focus at DVCon on its formal integrity verification platform for the RISC-V open-source which aims to speed up the core's adoption. The company will also feature the solution with a partner at EmbeddedWorld.
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February 21, 2019

DVCon USA 2019 preview: Metrics Technologies

Metrics Technologies demonstrate its cloud-based platform for ASIC and complex FPGA verification and discuss a new partnership with Concept Engineering.
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February 19, 2019

DVCon USA 2019 preview: Breker Verification Systems

The company will demonstrate the latest capabilities in its Trek5 portfolio, building on Accellera's Portable Stimulus Standard.
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February 19, 2019

DVCon USA 2019 preview: SmartDV

The verification IP specialist is focusing on its new products for RISC-V verification and for emulation platforms next week in San Jose.
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February 18, 2019

How to optimize your testbench-to-DUT connections

Testbench connections often depend on the virtual interface feature of SystemVerilog but other options - like abstract classes - can help.
February 11, 2019

DVCon USA 2019 preview: Mentor

DVCon USA is coming soon. Mentor's 2019 involvement includes a keynote from parent Siemens and a tutorial on managing your formal verification processes.
January 21, 2019

Synopsys gets big-chip signoff boost from Innovium

Data-centre networking chip goes through full-chip design rule checking and layout-versus-schematic signoff on TSMC's 16nm finFET process in a day.
January 21, 2019

Video series details the physical verification process

Physical verification challenge of large SoCs on leading-edge processes detailed in video series
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