Verification

July 30, 2020

Second formal check aids deadlock hunting

Arm works with EDA to find new efficiencies based on extra CTL-based check in Questa runs.
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July 20, 2020

FastSPICE upgrade boosts nano-scale analog verification by up to 10X

Mentor adds Analog FastSPICE eXTreme innovations for designs facing increasing parasitic complexity and contact resistance challenges at cutting edge nodes.
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May 28, 2020

Coverage without tears

A technical paper originally presented at DVCon USA 2020 simplifies the creation of coverage strategies using manual, automated and verification IP components.
May 15, 2020

Coronavirus Resources: Mentor

Live and on-demand videos as well as You Tube 'tips and techniques' clips form part of a wide 'work at home' support package from Mentor.
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April 23, 2020

Balancing PPA as machine learning moves to the edge

High-level synthesis is playing another important role in the matching of AI algorithms to necessarily application-specific designs.
April 22, 2020

Analyzing common resistance to deliver design reliability

Automated resistance checks mitigate the increasing complexity involved when analyzing voltage drop, ESD and noise, particularly for analog-heavy designs.
April 1, 2020

Coronavirus Resources: OneSpin Solutions

The verification specialist is adding more online resources to help engineers working from home during the Covid-19 pandemic.
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March 30, 2020

How to update legacy automotive designs for functional safety

Updates to existing designs are often error-prone, though safety tolerances are necessarily tightening. This four-step strategy can help.
March 19, 2020

Deploying pre- and post-silicon verification and test for 5G designs

A flexible and still evolving range of 5G standards requires methodologies that can handle massive test.
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March 3, 2020

DVCon US 2020: Coronavirus program changes

DVCon US 2020 is to end a day early as a result of the COVID-19 coronavirus outbreak and released an updated agenda.
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