The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.
Equivalence checking supports the efficient reuse of designs that reside on out-of-date silicon but remain valid in their own right.
5G IC designs have needed aggressive innovation across many elements and more use of FD-SOI that both pose parasitic extraction challenges.
Axiomise founder and formal expert Ashish Darbari will present across multiple events at DAC in San Francisco next week.
CXL is a strongly-backed technology aimed at improving connectivity across datacenters handling high demand HPC and AI applications.
Variable lifetimes are an apparently basic but also tricky feature within the verification language.
The NVMe 2.0 specification has introduced two namespace options that boost SSD performance while optimizing storage life.
Learn how to ingest data from multiple engineering teams in multiple formats on interposer and other multi-dimensional projects.
System Technology Co-optimization raises various SI, PI, thermal, mechanical and warp risks due to its use of advanced packaging. Early-stage prototyping mitigates them.
Silicon Photonics 3D integration posed LVS challenges in this fast emerging technical space. A case study describes how the two institutions overcame them.
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