Verification

Emulation is already playing a vital role in advanced automotive design within a digital twin environment.

The third part of this series takes the original CNN demonstrator through a full ISO 26262 type functional safety workflow

An object classification demonstrator shows how high-level synthesis (HLS) can speed the delivery and exploration of automotive design.

The new Calibre Reconnaissance feature within Mentor's physical verification suite aims to maximize compute resources and deliver manageable reports.

Reset domain crossing is another area where rising SoC complexity and IP reuse is causing an increase in reliability and safety challenges.

Konica Minolta describes how it has constructed a C++ signoff flow that mitigates code ambiguity, manual analysis and other inefficiencies.

ES Design West aims to help integrate the supply chain but also has plenty of engineering content aimed at low power, security, embedded and more.

The Bangalore conference has issued a last-minute call for panel proposals as technical paper submissions for the US edition get set to open next week.

A new paper describes an alternative to increasingly inefficient manual ESD verification that reduces risks of respins and missed delivery deadlines.

The verification IP is the first to become commercially available for the bus interface backed by companies such as AMD, Google, IBM, Micron and Xilinx.