Start-up launches platform on path to the specification, emulation and simulation of large chiplet-based designs.
Solido discusses how it has leveraged AI for SPICE level efficiency and the benchmarks it has used.
What are your options and what is one of the latest simulator features that helps streamline your build?
South Korea's leading research institute has built a reusable flow for lower power petaflops-performance AI.
Chiplet-based 3DIC designs present new challenges for flows that integrate tasks from design exploration to physical verification.
Just how much of the flow has already has 'shift left' benefit and what is fueling further progress.
The Joules RTL Design Studio aims to make coding more aware of aware of physical issues before and after hand-off for implementation.
Calibre Design Enhancer moves physical verification checks and automated DRC-clean via and cell insertion into P&R
Three fast developing AI techniques underpin the efficiencies in the new Solido custom design and verification platform.
The company says the mixed-signal platform enabled a 5X improvement in verification productivity.
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