September 8, 2022
The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.
September 8, 2022
Equivalence checking supports the efficient reuse of designs that reside on out-of-date silicon but remain valid in their own right.
September 5, 2022
5G IC designs have needed aggressive innovation across many elements and more use of FD-SOI that both pose parasitic extraction challenges.
July 7, 2022
Axiomise founder and formal expert Ashish Darbari will present across multiple events at DAC in San Francisco next week.
June 28, 2022
CXL is a strongly-backed technology aimed at improving connectivity across datacenters handling high demand HPC and AI applications.
April 29, 2022
Variable lifetimes are an apparently basic but also tricky feature within the verification language.
April 27, 2022
The NVMe 2.0 specification has introduced two namespace options that boost SSD performance while optimizing storage life.
February 10, 2022
Learn how to ingest data from multiple engineering teams in multiple formats on interposer and other multi-dimensional projects.
February 8, 2022
System Technology Co-optimization raises various SI, PI, thermal, mechanical and warp risks due to its use of advanced packaging. Early-stage prototyping mitigates them.
January 25, 2022
Silicon Photonics 3D integration posed LVS challenges in this fast emerging technical space. A case study describes how the two institutions overcame them.