Refining DTCO to bridge data walls in system design
DTCO (design technology co-optimization) looks to address systemic verification challenges but the process still needs to be extended.
Verification
Early package assembly verification for faster, better results
Make it easier to capture issues in 2.5D and 3D designs with multiple chiplets and emerging challenges with this 'shift left' approach.
Take a deeper dive into BCI-ROM
A new paper looks at examples for using The Boundary Condition Independent Reduced Order Model (BCI-ROM) in its VHDL-AMS implementation for electro-thermal analysis.
Zero ASIC open sources system simulation/emulation platform
Start-up launches platform on path to the specification, emulation and simulation of large chiplet-based designs.
Benchmarking the maturity of AI in EDA
Solido discusses how it has leveraged AI for SPICE level efficiency and the benchmarks it has used.
Creating the right simulation build flow
What are your options and what is one of the latest simulator features that helps streamline your build?
ETRI builds flow for AI chiplets
South Korea's leading research institute has built a reusable flow for lower power petaflops-performance AI.
Flow evolution for the 3DIC/chiplet age
Chiplet-based 3DIC designs present new challenges for flows that integrate tasks from design exploration to physical verification.
Catch up with the state-of-the-art in ‘shift left’
Just how much of the flow has already has 'shift left' benefit and what is fueling further progress.
Cadence mixes know-how and AI to bridge RTL gap
The Joules RTL Design Studio aims to make coding more aware of aware of physical issues before and after hand-off for implementation.