The formal apps start-up has built strong positions in automotive and RISC-V and will strengthen Siemens in competition with Cadence.
Electrostatic discharge verification is becoming increasingly hard to achieve but automated pre-loaded checks can now help.
Virtual strategies make for greater productivity and widen the number of emulation use cases. A new paper considers some of the most popular examples.
Originally presented at DVCon Europe, a new paper automates complex steps in RDC verification and reduces noise.
Computational storage devices are posing a new raft of challenges that is being addressed using a powerful pre-silicon methodology.
Study may point to new challenges in more bidirectional AMS implementations on SoC-class designs, though formal and emulation help keep respin count in check.
Less than one-in-five FPGA projects avoid bug escapes (Wilson Functional Verification 2020 – Part Two)
Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.
Use of the open-source RISC-V processor was tracked for the first time by the biennial study, finding notably high take-up.
A partnership between Siemens and VSI, a real-world autonomous vehicle research company, aims to refine and promote digital twin strategies.
The free-to-attend user meetings for Mentor clients will retain the same format mixing technical presentations with keynotes and networking.
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