Arm works with EDA to find new efficiencies based on extra CTL-based check in Questa runs.
Mentor adds Analog FastSPICE eXTreme innovations for designs facing increasing parasitic complexity and contact resistance challenges at cutting edge nodes.
A technical paper originally presented at DVCon USA 2020 simplifies the creation of coverage strategies using manual, automated and verification IP components.
Live and on-demand videos as well as You Tube 'tips and techniques' clips form part of a wide 'work at home' support package from Mentor.
High-level synthesis is playing another important role in the matching of AI algorithms to necessarily application-specific designs.
Automated resistance checks mitigate the increasing complexity involved when analyzing voltage drop, ESD and noise, particularly for analog-heavy designs.
The verification specialist is adding more online resources to help engineers working from home during the Covid-19 pandemic.
Updates to existing designs are often error-prone, though safety tolerances are necessarily tightening. This four-step strategy can help.
A flexible and still evolving range of 5G standards requires methodologies that can handle massive test.
DVCon US 2020 is to end a day early as a result of the COVID-19 coronavirus outbreak and released an updated agenda.
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