low-power design

Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.

An object classification demonstrator shows how high-level synthesis (HLS) can speed the delivery and exploration of automotive design.

Mary Jane Irwin of Penn State University has been named as the first female recipient of the Phil Kaufman Award for contributions to electronic design.

Embedded magnetic RAM is emerging as a contender for on-chip memory not just from a density standpoint but from that of power.

For nVidia chief scientist and Stanford professor Bill Dally, now is a great time to be involved in hardware design, thanks to the rise of AI.

UPF power state tables have become unwieldy due to rapid growth in LP design. The new construct, 'add_power_state' enables better verification flows.

EEMBC has released a benchmark and initial results that analyze peripheral performance on microcontrollers.

Sonics has developed a version of its power-management IP core for SoCs that adds support for dynamic voltage and frequency scaling, along with the ability to tune settings according to temperature.

An ESD Alliance panel on incoming Californian energy regulations originally scheduled for later this month has been postponed.

Xilinx plans to add high-speed analog interfaces to its upcoming FPGAs to better support high-density 5G basestation designs.