low-power design

October 2, 2019

Master the design and verification of next gen transport: Part Two – high-level synthesis

An object classification demonstrator shows how high-level synthesis (HLS) can speed the delivery and exploration of automotive design.
October 1, 2019

Low-power pioneer to receive 2019 Kaufman Award

Mary Jane Irwin of Penn State University has been named as the first female recipient of the Phil Kaufman Award for contributions to electronic design.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations: ,
December 12, 2018

IEDM shows progress on embedded eMRAM

Embedded magnetic RAM is emerging as a contender for on-chip memory not just from a density standpoint but from that of power.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations: , , ,
June 21, 2018

AI is all about low-energy hardware says Dally

For nVidia chief scientist and Stanford professor Bill Dally, now is a great time to be involved in hardware design, thanks to the rise of AI.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , , , ,   |  Organizations: ,
December 6, 2017

Learn how to simplify power states in UPF

UPF power state tables have become unwieldy due to rapid growth in LP design. The new construct, 'add_power_state' enables better verification flows.
Article  |  Topics: Blog - EDA, - Standards, Verification  |  Tags: , , ,   |  Organizations: , , ,
September 12, 2017

MCU benchmark homes in on peripheral power

EEMBC has released a benchmark and initial results that analyze peripheral performance on microcontrollers.
Article  |  Topics: Blog - Embedded  |  Tags: , , ,   |  Organizations: , ,
June 27, 2017

Sonics adds heat-aware DVFS to SoC power controller

Sonics has developed a version of its power-management IP core for SoCs that adds support for dynamic voltage and frequency scaling, along with the ability to tune settings according to temperature.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations: ,
March 7, 2017

POSTPONED: Get to grips with new PC, monitor energy regs

An ESD Alliance panel on incoming Californian energy regulations originally scheduled for later this month has been postponed.
Article  |  Topics: Blog - EDA, - Standards  |  Tags:   |  Organizations: , , , , , ,
February 21, 2017

Xilinx to bring analog conversion onto finFET FPGAs

Xilinx plans to add high-speed analog interfaces to its upcoming FPGAs to better support high-density 5G basestation designs.
Article  |  Topics: Blog - Embedded, PCB  |  Tags: , , , , ,   |  Organizations: ,
June 9, 2016

2D tools adapt to create smaller monolithic 3DIC designs

Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors