Standards

January 21, 2024

Take a deeper dive into BCI-ROM

A new paper looks at examples for using The Boundary Condition Independent Reduced Order Model (BCI-ROM) in its VHDL-AMS implementation for electro-thermal analysis.
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November 23, 2021

DAC 2021 Preview: Siemens EDA

DAC 2021 is looming and here is our first round up of a major EDA player's plans for the physical event in San Francisco.
August 18, 2021

Overcome reset domain crossing challenges when using UPF

A DVCon technical paper addresses potential reset domain crossing metastability issues due to UPF instrumentation.
May 19, 2021

Understand how DO-254 defines verification for avionics

The avionics design assurance guidance has its own flavor of verification which needs to be understood alongside its definition of validation.
February 15, 2021

Getting a RISC-V embedded toolchain in place

A new white paper reviews the history of the open-source platform and provides guidance on best practice development for embedded.
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November 27, 2020

RISC-V in nearly a quarter of designs (Wilson Functional Verification 2020 – Part One)

Use of the open-source RISC-V processor was tracked for the first time by the biennial study, finding notably high take-up.
February 24, 2020

DVCon US 2020 preview: Mentor

Mentor will have a very broad presence at DVCon across technologies such as HLS, formal verification, simulation and emulation.
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July 5, 2019
ES Design West logo

The road to ES Design West: Design Pavilion

ES Design West aims to help integrate the supply chain but also has plenty of engineering content aimed at low power, security, embedded and more.
April 2, 2019

DVCon China 2019 preview: SmartDV

RISC-V VIP offerings headline the verification specialist’s presence in Shanghai later this month.
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March 26, 2019

UVM Cookbook released in new edition

Popular Verification Academy manual revamped and updated to bring it more closely in line with IEEE 1800.2 UVM and reflect the increasing use of emulation.
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