Standards

A new paper looks at examples for using The Boundary Condition Independent Reduced Order Model (BCI-ROM) in its VHDL-AMS implementation for electro-thermal analysis.

DAC 2021 is looming and here is our first round up of a major EDA player's plans for the physical event in San Francisco.

A DVCon technical paper addresses potential reset domain crossing metastability issues due to UPF instrumentation.

The avionics design assurance guidance has its own flavor of verification which needs to be understood alongside its definition of validation.

A new white paper reviews the history of the open-source platform and provides guidance on best practice development for embedded.

Use of the open-source RISC-V processor was tracked for the first time by the biennial study, finding notably high take-up.

Mentor will have a very broad presence at DVCon across technologies such as HLS, formal verification, simulation and emulation.

ES Design West aims to help integrate the supply chain but also has plenty of engineering content aimed at low power, security, embedded and more.

RISC-V VIP offerings headline the verification specialist’s presence in Shanghai later this month.

Popular Verification Academy manual revamped and updated to bring it more closely in line with IEEE 1800.2 UVM and reflect the increasing use of emulation.