AI’s possible roles in verification covered at VF2023
The recent Verification Futures Europe conference looked at what AI, from decision trees to foundation models, could do to speed up RTL checks.
Synopsys
Imperas and Synopsys team on RISC-V debug
Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
Semiwise brings cryogenic models to SOI
Semiwise has developed transistor models for the GlobalFoundries 22FDX that cover operation at cryogenic temperatures.
Saber models aim for ADI power chips
Synopsys and Analog Devices have agreed to provide model libraries for the chipmaker's DC/DC ICs and power regulators that work with the Saber simulation tool.
Synopsys talks AI in verification at DVCon
Synopsys R&D vice president Manish Pandey described the ways in which the tools supplier has harnessed machine learning so far to gain speedups and improvements in coverage.
UK consortium starts work on cryogenic CMOS
A £6.5m grant will fund the development of memories and other IP to improve the control of qubits in quantum computers.
Python provides the link for speed checks at Sondrel
Sondrel has combined EDA tools with custom SystemC and Python code to develop a system that can help automate the detailed performance analysis of high-level architectures before RTL is generated.
Synopsys claims 35TOPS performance from new family of embedded vision cores
IP core focuses on avodiing memory access bottlenecks during processing of complex machine-learning and artificial-intelligence algortihms.
The road to ES Design West: Design Pavilion
ES Design West aims to help integrate the supply chain but also has plenty of engineering content aimed at low power, security, embedded and more.
IoT ecosystems should shift to cellular connectivity for security – report
IoT ecosystems should shift from WiFi to cellular connectivity to make them easier to secure and manage.