Heterogeneous integration has the potential to overcome the yield and cost challenges presented by the growing headwinds associated with process scaling. But it may take a dramatic rethink in design approaches.
In a panel session at VLSI Symposia, AMD described how the economics have come down strongly in favor of multichip integration for multicore server processors.
Waferscale SSDs are among the future drive architectures being explored by Kioxia, according to a keynote delivered at VLSI Symposia.
As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.
Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
Having provided a forum for describing the progress of process technology and circuit design for four decades, the organizers of the 2020 Symposia on VLSI Technology & Circuits are asking presenters to look at the coming 40 years.
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