Building an ecosystem around HLS for AI and ML designs
Mentor's AI Accelerator Ecosystem adds reference designs, libraries and other forms of support around its Catapult HLS platform.
FPGA
DAC 2019 preview: OneSpin Solutions
OneSpin is bringing recent product launches to DAC and will have technical experts presenting within the conference's Designer Track.
OneSpin extends line-up for AI FPGA and RISC-V verification
The formal specialist is extending its line for Intel FPGAs that target areas such as AI/ML and HPC, and building out a RISC-V suite focused on ISA compliance.
Achronix deploys network on chip for faster FPGAs
Achronix is introducing an FPGA architecture that pulls a full network-on-chip into the programmable-logic fabric combined with hardened matrix-math processors for AI.
DVCon USA 2019 preview: Metrics Technologies
Metrics Technologies demonstrate its cloud-based platform for ASIC and complex FPGA verification and discuss a new partnership with Concept Engineering.
Microchip opts for RISC-V cores in SoC FPGA
Microsemi has put multiple RISC-V cores into a new generation of SoC FPGAs, intended for embedded systems that need to run Linux.
FPGA playing verification catch-up as bugs escape
The latest Mentor-commissioned Wilson Research Group study on ASIC and FPGA verification highlights technique adoption and maturity.
Embedded FPGAs start to take hold in SoC
The embedded FPGA is beginning to find a market, with communications leading the way but machine learning likely to drive further adoption.
Mixed-signal circuits push scaled CMOS at VLSI
The circuits sessions at mid-June's VLSI Symposia in Honolulu feature a number of papers that improve the performance of scaled mixed-signal processes.
Xilinx plans reconfigurable compute for 7nm FPGA generation
Xilinx plans to make reconfigurable computing the focus of its upcoming generation of FPGAs, which will be made on a 7nm finFET process at TSMC and expected to start sampling next year.
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