Equivalence checking supports the efficient reuse of designs that reside on out-of-date silicon but remain valid in their own right.
A detailed technical overview of formal verification within the context of the DO-254 (ED-80) standard is now available to download.
Xilinx has reworked its Versal FPGA for edge-AI applications.
The formal apps start-up has built strong positions in automotive and RISC-V and will strengthen Siemens in competition with Cadence.
Less than one-in-five FPGA projects avoid bug escapes (Wilson Functional Verification 2020 – Part Two)
Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.
Xilinx has released the first version of its Vitis development environment as the company aims to capture a user base that is more used to software than hardware tools.
The US Quantum Economic Development Consortium is looking to stimulate a supply chain and technology infrastructure for quantum computing, with more about its efforts due to come out in the next few days.
Mentor's AI Accelerator Ecosystem adds reference designs, libraries and other forms of support around its Catapult HLS platform.
OneSpin is bringing recent product launches to DAC and will have technical experts presenting within the conference's Designer Track.
The formal specialist is extending its line for Intel FPGAs that target areas such as AI/ML and HPC, and building out a RISC-V suite focused on ISA compliance.
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