functional verification

August 22, 2023

Accellera group formed to work on federated simulation

Accellera has formed a working group to look at the possibility of creating a standard for federated simulation.
July 11, 2023

AI’s possible roles in verification covered at VF2023

The recent Verification Futures Europe conference looked at what AI, from decision trees to foundation models, could do to speed up RTL checks.
May 30, 2023

Charting the path for machine learning in functional verification

A comprehensive review of ML's potential and its current use identifies challenges ahead.
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April 25, 2023

Alps Alpine composes capacitance IC with Symphony

The company says the mixed-signal platform enabled a 5X improvement in verification productivity.
April 17, 2023

DVCon Europe adds research track

DVCon Europe is expanding coverage into research on design verification for its 10th conference later this year.
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February 28, 2023

Imperas and Synopsys team on RISC-V debug

Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
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September 15, 2022

Cadence extends AI to verification data with unified database

Cadence has brought the inputs for its AI-driven tools under the umbrella of a big-data collection platform and added functional verification to the list of products that use machine learning.
August 3, 2022

Imperas releases RISC-V coverage library as open source

Imperas Software has published an open-source functional-coverage library for RISC-V cores.
July 14, 2022

‘Shocking’ quality sees vendors organize around RISC-V verification

Three EDA vendors team up to create stronger verification flow for RISC-V processor implementations.
April 7, 2021

Accellera publishes security standard draft

Accellera has published the version 1.0 draft of the proposed Security Annotation for Electronic Design Integration standard.
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