Accellera group formed to work on federated simulation
Accellera has formed a working group to look at the possibility of creating a standard for federated simulation.
functional verification
AI’s possible roles in verification covered at VF2023
The recent Verification Futures Europe conference looked at what AI, from decision trees to foundation models, could do to speed up RTL checks.
Charting the path for machine learning in functional verification
A comprehensive review of ML's potential and its current use identifies challenges ahead.
Alps Alpine composes capacitance IC with Symphony
The company says the mixed-signal platform enabled a 5X improvement in verification productivity.
DVCon Europe adds research track
DVCon Europe is expanding coverage into research on design verification for its 10th conference later this year.
Imperas and Synopsys team on RISC-V debug
Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
Cadence extends AI to verification data with unified database
Cadence has brought the inputs for its AI-driven tools under the umbrella of a big-data collection platform and added functional verification to the list of products that use machine learning.
Imperas releases RISC-V coverage library as open source
Imperas Software has published an open-source functional-coverage library for RISC-V cores.
‘Shocking’ quality sees vendors organize around RISC-V verification
Three EDA vendors team up to create stronger verification flow for RISC-V processor implementations.
Accellera publishes security standard draft
Accellera has published the version 1.0 draft of the proposed Security Annotation for Electronic Design Integration standard.
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