Cadence has brought the inputs for its AI-driven tools under the umbrella of a big-data collection platform and added functional verification to the list of products that use machine learning.
Imperas Software has published an open-source functional-coverage library for RISC-V cores.
Three EDA vendors team up to create stronger verification flow for RISC-V processor implementations.
Accellera has published the version 1.0 draft of the proposed Security Annotation for Electronic Design Integration standard.
The best paper awards at this month's DVCon highlighted techniques to streamline verification. The European version in the meantime is looking for paper submissions.
Accellera Systems Initiative has published for open review version 2.0 of the Portable Test and Stimulus standard.
Speakers at this year's DVCon Europe called on the hardware community to find inspiration in software-development trends.
Functional verification for increasingly complex ARM-based designs is at the heart of the new consultancy partnership.
Developing a security assurance standard for IP faces numerous problems but Accellera working-group members are trying to find an answer.
In a panel session at June's DAC, Synopsys customers talked about some of the ways they make verification more efficient and bring technologies such as formal, emulation, and simulation together.
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