February 8, 2024
Accellera has formed a working group to look at extensions to SystemVerilog to improve support for mixed-signal designs.
January 12, 2024
Workshops on portable stimulus, functional safety, verification of RISC-V processors, and design with chiplets and large language models will feature at the upcoming 2024 DVCon US.
October 16, 2023
Accellera ’s board of directors has approved the version 2.1 of the Portable Test and Stimulus Standard.
October 6, 2023
MachineWare has expanded its portfolio of high-speed instruction-set simulators to the Arm Cortex-A and -M architectures.
August 22, 2023
Accellera has formed a working group to look at the possibility of creating a standard for federated simulation.
July 11, 2023
The recent Verification Futures Europe conference looked at what AI, from decision trees to foundation models, could do to speed up RTL checks.
May 30, 2023
A comprehensive review of ML's potential and its current use identifies challenges ahead.
April 25, 2023
The company says the mixed-signal platform enabled a 5X improvement in verification productivity.
April 17, 2023
DVCon Europe is expanding coverage into research on design verification for its 10th conference later this year.
February 28, 2023
Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.