Accellera forms working group for mixed-signal interfaces
Accellera has formed a working group to look at extensions to SystemVerilog to improve support for mixed-signal designs.
functional verification
DVCon gears up for March in San Jose
Workshops on portable stimulus, functional safety, verification of RISC-V processors, and design with chiplets and large language models will feature at the upcoming 2024 DVCon US.
Accellera updates portable stimulus standard
Accellera ’s board of directors has approved the version 2.1 of the Portable Test and Stimulus Standard.
Fast instruction simulator expands to Arm
MachineWare has expanded its portfolio of high-speed instruction-set simulators to the Arm Cortex-A and -M architectures.
Accellera group formed to work on federated simulation
Accellera has formed a working group to look at the possibility of creating a standard for federated simulation.
AI’s possible roles in verification covered at VF2023
The recent Verification Futures Europe conference looked at what AI, from decision trees to foundation models, could do to speed up RTL checks.
Charting the path for machine learning in functional verification
A comprehensive review of ML's potential and its current use identifies challenges ahead.
Alps Alpine composes capacitance IC with Symphony
The company says the mixed-signal platform enabled a 5X improvement in verification productivity.
DVCon Europe adds research track
DVCon Europe is expanding coverage into research on design verification for its 10th conference later this year.
Imperas and Synopsys team on RISC-V debug
Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.