August 22, 2023
Accellera has formed a working group to look at the possibility of creating a standard for federated simulation.
July 11, 2023
The recent Verification Futures Europe conference looked at what AI, from decision trees to foundation models, could do to speed up RTL checks.
May 30, 2023
A comprehensive review of ML's potential and its current use identifies challenges ahead.
April 25, 2023
The company says the mixed-signal platform enabled a 5X improvement in verification productivity.
April 17, 2023
DVCon Europe is expanding coverage into research on design verification for its 10th conference later this year.
February 28, 2023
Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
September 15, 2022
Cadence has brought the inputs for its AI-driven tools under the umbrella of a big-data collection platform and added functional verification to the list of products that use machine learning.
August 3, 2022
Imperas Software has published an open-source functional-coverage library for RISC-V cores.
July 14, 2022
Three EDA vendors team up to create stronger verification flow for RISC-V processor implementations.
April 7, 2021
Accellera has published the version 1.0 draft of the proposed Security Annotation for Electronic Design Integration standard.