Accellera has formed a working group to look at the possibility of creating a standard for federated simulation.
The recent Verification Futures Europe conference looked at what AI, from decision trees to foundation models, could do to speed up RTL checks.
A comprehensive review of ML's potential and its current use identifies challenges ahead.
The company says the mixed-signal platform enabled a 5X improvement in verification productivity.
DVCon Europe is expanding coverage into research on design verification for its 10th conference later this year.
Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
Cadence has brought the inputs for its AI-driven tools under the umbrella of a big-data collection platform and added functional verification to the list of products that use machine learning.
Imperas Software has published an open-source functional-coverage library for RISC-V cores.
Three EDA vendors team up to create stronger verification flow for RISC-V processor implementations.
Accellera has published the version 1.0 draft of the proposed Security Annotation for Electronic Design Integration standard.
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