Both 3D IC and 2.5D IC techniques are being used on more designs and the DFT infrastructure is evolving to meet the challenges they pose.
SLS brings the power of product lifecycle management to the increasingly complex oversight challenges in electronic systems design.
A new technique is especially efficient for AI chips with modular, tiled design strategies leveraging multiple instantiations of the same cores.
The world of ATPG just changed with the introduction of a new way to create and choose the most effective test patterns.
It is easier than ever to build a flexible, resilient, and end-to-end hierarchical DFT flow with smart automation.
Learn how the latest design for test innovations deliver efficiency and profitability across the design flow.
It's the fiftieth International Test Conference this year. How much has been achieved and how much more work is there to do to ensure that we can keep building chips that do what they are supposed to?
SEMICON West showed a distinct thematic shift away from preserving Moore's Law to assessing the architectural implications of AI, as EDA was brought into the event.
Hierarchical DFT for Arm-based SoCs is easier than ever with the arrival of a complete reference flow from Mentor and Arm.
Part two of this feature describes three use-cases that exploit the VirtuaLAB technology in HDMI, PCIe and Ethernet designs.
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