Assembly & Integration

March 26, 2019

High-level synthesis for AI: Part One

The computational and algorithmic demands made by computer vision systems highlight HLS' value for AI system development.
March 15, 2019

Enabling the move to a system-centric view

Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.
March 1, 2019

Accelerating the implementation of application-specific processors

Application-specific processors can provide high performance for specialised tasks at low energy cost.
October 16, 2018
Reliability verification feature - featured image

Reliability verification: It’s all about the baseline

How you can use the dedicated rule decks now being provided by foundries as the foundation for a reliability verification flow.
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August 13, 2018
Dina Medhat is a Technical Lead for Calibre Design Solutions at Mentor, a Siemens Business. She has held a variety of product and technical marketing roles at the company, and received her BS and MS degrees from Ain Shames University in Cairo, Egypt. She is currently a PhD student at Ain Shames University.

Managing waivers in reliability verification

Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.
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April 23, 2018

How eFPGAs will help build the brave new world of AI

Artificial intelligence and machine learning require the performance and flexibility offered by embedded FPGA (eFPGA) technology.
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March 29, 2018
Two wafers fabbed at Imec

3DIC technology provides performance boosts

3D integration technology has split into a number of different approaches, each of which brings a different combination of benefits in terms of performance.
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October 14, 2017
Michael Chen is Director, Design for Security, in the New Ventures Division of Mentor, a Siemens Business.

Making security a profit center for silicon

The assumption has been that extra security eats into profit margins. But with some lateral thinking it can actually improve the bottom line.
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September 8, 2017

How HLS is giving shape to glasses-free 3DTV

High level synthesis (HLS) was adopted to realize innovative display IP as developed by a small core engineering team.
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August 7, 2017
Pedro Ricardo Miguel

Supporting higher-resolution displays without major system redesign

Using VESA's Display Stream Compression (DSC) standard to enable visually lossless performance and low latency for ultra-high-definition displays.
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