AI aims to cut CAD-model generation time
Ultra Librarian has developed an AI-driven CAD modeling engine that should slash the the time it takes to build component and subsystem models for PCB layout and system design.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
Cadence gives OrCAD access to cloud AI placement
Cadence has given its new release of OrCAD access to the cloud-based AI placer designed for its Allegro PCB-layout software.
HPC and AI provide keynote focus at DVCon Europe
DVCon Europe has announced its two keynote presentations, focusing on energy-efficient high-performance computing and machine learning.
Accellera group formed to work on federated simulation
Accellera has formed a working group to look at the possibility of creating a standard for federated simulation.
Catch up with the state-of-the-art in ‘shift left’
Just how much of the flow has already has ‘shift left’ benefit and what is fueling further progress.
Verification Futures heads to the US in September
Tessolve is bringing its Verification Futures conference to the US with an event scheduled for mid-September.
Backside power shows promise but more complex manufacturing
Backside power delivery could lead to improvements in chip density and more straightforward place-and-route phases according to work presented at this year’s VLSI Symposium.
Ferroelectric memory moves closer with VLSI experiments
Ferroelectric memory may be able to stage a comeback thanks to materials innovations as work presented at VLSI Symposium have shown, though there is still plenty to do.
Cadence mixes know-how and AI to bridge RTL gap
The Joules RTL Design Studio aims to make coding more aware of aware of physical issues before and after hand-off for implementation.
‘Two wafers are better than one’ for 3D flash
Western Digital’s head of technology set out at the recent VLSI Symposium the ways in which flash makers can scale without costs accelerating.
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