Ultra Librarian has developed an AI-driven CAD modeling engine that should slash the the time it takes to build component and subsystem models for PCB layout and system design.
Cadence has given its new release of OrCAD access to the cloud-based AI placer designed for its Allegro PCB-layout software.
DVCon Europe has announced its two keynote presentations, focusing on energy-efficient high-performance computing and machine learning.
Accellera has formed a working group to look at the possibility of creating a standard for federated simulation.
Just how much of the flow has already has ‘shift left’ benefit and what is fueling further progress.
Tessolve is bringing its Verification Futures conference to the US with an event scheduled for mid-September.
Backside power delivery could lead to improvements in chip density and more straightforward place-and-route phases according to work presented at this year’s VLSI Symposium.
Ferroelectric memory may be able to stage a comeback thanks to materials innovations as work presented at VLSI Symposium have shown, though there is still plenty to do.
The Joules RTL Design Studio aims to make coding more aware of aware of physical issues before and after hand-off for implementation.
Western Digital’s head of technology set out at the recent VLSI Symposium the ways in which flash makers can scale without costs accelerating.
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