Imperas Software has published an open-source functional-coverage library for RISC-V cores.
Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.
Teledyne e2v has demonstrated a prototype optical link that the company believes could replace electrical signaling for remote RF heads.
As the project that funded OpenRoad draws to a close, experts pondered its wider future at the 59th DAC.
Three EDA vendors team up to create stronger verification flow for RISC-V processor implementations.
Siemens has launched Calibre DRC engines that make it easier to perform useful checks early in the layout process.
Cadence president expects expanded role for reinforcement learning in tool portfolio and looks for help on AI for verification.
Siemens EDA has launched a second version of its Symphony simulation environment designed to support quicker debug cycles.
Thermal-simulation specialist Future Facilities has agreed to be acquired by Cadence Design Systems.
Agile Analog’s oscillator IP sees the company focus on IP created with its own circuit creation and porting tool.
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