Three EDA vendors team up to create stronger verification flow for RISC-V processor implementations.
Breker Verification Systems
Breker's presence at next week's Design Automation Conference (DAC) will emphasize a new collaboration around the RISC-V platform.
Breker will highlight its latest work on stress-testing processor, storage and I/O architectures during DAC 2021 this week.
In a panel at this week’s DVCon Europe, experts described a number of issues facing teams looking to incorporate machine learning in logic verification flows and why some of those efforts will not pay off while others succeed.
Breker has added a number of specialized apps to its library that deal with the verification of RISC-V processors, secure enclaves, and machine-learning designs.
Portable stimulus pioneer Breker will feature across the DVCon program also highlighting its work with RISC-V.
App joins Portable Stimulus specialist's Trek5 family to reduce manual test writing during verification on designs for the fast-growing RISC-V open-source processor.
ES Design West aims to help integrate the supply chain but also has plenty of engineering content aimed at low power, security, embedded and more.
The company will highlight features within its Trek suite that comply with but then go beyond the capabilities of the Portable Stimulus Standard.
Breker CEO Adnan Hamid will lead a tutorial on the Portable Stimulus Standard as part of the verification specialist's activities in Shanghai.
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