Hit your tapeout schedules with in-design signoff DRC
Delivering physical implementations at new process nodes is getting ever harder. Learn how to stay on track by checking work is rule-compliant as you go.
IC Implementation
Out-of-sync data issues in parallel design flows need automated design integrity checks
Overcome problems created by mismatches between library exchange format (LEF) and GDS or OASIS representations to avoid design delays.
How you can decide what level of DRC you need when you need it
Using on-demand rule checks during place-and-route boosts efficiency and design quality.
DVCon Europe best paper assesses clock design
The best paper at DVCon Europe 2020 analyzed different multiclock strategies for SoCs for their power and flexibility
The path to full functional monitoring
Joe Sawicki of Siemens EDA recently addressed the main trends in design delivery from architecture to validation to digital twins - and where they may soon take the industry and its products.
Silicon lifecycle solutions help you listen to your chip
SLS brings the power of product lifecycle management to the increasingly complex oversight challenges in electronic systems design.
P&R filler cell insertion slowing you down? Replace it
A physical verification-ready flow can speed project delivery by making your use of filler cells more efficient.
How to achieve fast, automated, sign-off verification of DFM hotspot fixes in P&R
A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.
How cloud computing is now delivering efficiencies for IC design
A Mentor-Microsoft-AMD pathfinder demonstrates the potential benefits of cloud-based physical verification.
How automated power/ground short checks slash time during implementation
Early detection using design integrity checks during implementation from abstract LEF/DEF inputs can deliver major efficiencies.
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