DFM

October 19, 2023
Neel Natekar is a senior product engineer in the Design to Silicon division of Siemens Digital Industries Software. Prior to joining Siemens, Neel worked as a design engineer focusing on power delivery solutions for custom CPUs. He received a B.Eng. in Electronics and Telecommunications from the University of Mumbai, and an M.S. in Electrical Engineering, Circuits and Microsystems from the University of Michigan.

Simplify and accelerate PV debug using default results data views

Standard physical verification (PV) check reviews within EDA tools can reduce time-to-tapeout and mitigate risk.
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August 8, 2023
Jeff Wilson is a Product Management Director for DFM applications in the Calibre Design solutions organization at Siemens Digital Industries Software. Before joining Siemens, Jeff worked at Motorola and SCS. He holds a B.Sc. in design engineering from Brigham Young University and an MBA from the University of Oregon.

Improved power management and faster time to market?

We have the technology. Learn how to 'shift left' with Calibre DesignEnhancer and meet IR, EM and PPA objectives.
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May 16, 2023
Oasis P39 Semi

Six reasons why you need better cross-platform validation of OASIS layout database generation

You must understand six comparison concerns and their effect on database equivalency. Adopt a solution with an in-depth object-based approach.
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January 26, 2023
3D IC workflow democratization

Give the people what they want: toward making 3D IC mainstream

Learn more about the five interconnected workflows that are democratizing next generation design in the emerging chiplet age.
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October 6, 2022
3D-IC Stack LVS Connectivity

Building confidence and flexibility in 3D-IC system level design

3D-IC presents major connectivity challenges in maintaining a golden netlist and managing necessary exceptions. Learn how to manage them.
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May 10, 2022
Coordinate-based checks feature

A quick and easy way to calculate P2P resistance and current density

Coordinate-based checking provides a streamlined way to verify designs around ESD before full-chip runs without the need for custom checks.
April 28, 2022
James Paris is a senior product engineer with the Design to Silicon division of Siemens Digital Industries Software, supporting Calibre design interfaces. Prior to joining Siemens, he held roles in analog/mixed-signal physical design implementation and flow development for various IC design companies. James holds a BS in Computer-Aided Design Engineering and an MBA in Marketing.

Layout customization improves productivity in design and verification flows

What are the options and how do you balance overarching CAD requirements and personal preferences?
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January 13, 2022

Siemens’ Sawicki puts priority on scaling in processes, productivity and systems

More optimistic about the semiconductor industries prospects than for some time, Siemens Joe Sawicki identified key EDA challenges at DAC.
November 12, 2021
Pre-processing and post-processing techniques for verification

How to optimize productivity and accuracy in IC design and verification flows

Pre- and post-processing EDA techniques help streamline design rule checks and delivery efficient waivers to speed design and debug.
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September 13, 2021
Swathi Rangarajan is a principal product engineer in the Calibre Design Solutions division of Siemens Digital Industries Software, supporting the Calibre RealTime platform. She focuses on in-design sign-off Calibre DRC checking in custom and digital design tools. Before joining Siemens, Swathi was an application engineer focusing on custom and digital design tool suites. Swathi received her BS in electronics and communication engineering from India, and her MS in engineering from San Jose State University

Hit your tapeout schedules with in-design signoff DRC

Delivering physical implementations at new process nodes is getting ever harder. Learn how to stay on track by checking work is rule-compliant as you go.
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