This case study shows how rising CMP simulation quality can be leveraged to detect the position and type of planarity hotspots before manufacture and verify the planarity of a layout.
The RF and AMS specialist turned to design software that allowed it to run design checks during place and route.
Master the three prerequisites of format translation and chose the right one from the various translation strategies.
SEMICON West showed a distinct thematic shift away from preserving Moore's Law to assessing the architectural implications of AI, as EDA was brought into the event.
Whether you use OASIS or GDSII, unwanted duplicate cells can make their way into the final SoC database. Learn how to remove them.
How Mentor develops and works with partners to prepare each version of its Calibre DFM platform to be ready for the introduction of each new process node.
CAA is a valuable tool available to both design engineers and foundries to help them avoid layout-dependent effects during manufacturing.
Automated voltage-aware DRC addresses the reliability verification challenges in today’s high-voltage and multiple power domain applications.
Machine learning techniques help ensure the validity of Liberty Variation Format information for OCV analysis at lower process nodes.
How to achieve efficient merging of data from formats such as OASIS, GDS, and OpenAccess to ensure timely verification through DRC runs.
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