Would you prefer a hypervisor or a multicore framework?
Determining which embedded technique to adopt is more than just a question of what cores the system has.
architecture
Master the design and verification of next gen transport: Part Two – high-level synthesis
An object classification demonstrator shows how high-level synthesis (HLS) can speed the delivery and exploration of automotive design.
Roadmapping the quantum realm
The US Quantum Economic Development Consortium is looking to stimulate a supply chain and technology infrastructure for quantum computing, with more about its efforts due to come out in the next few days.
Mentor’s 2015 Valley User2User is less than two weeks away
IoT-themed keynotes from Mentor's Wally Rhines and Qualcomm's Karim Arabi headline vendor's User2User conference on April 21.
New flows needed for the ‘insects of the SoC world’
Chris Rowen, CTO of the IP group at Cadence Design Systems, expects the internet of things (IoT) to cause a split in approaches to SoC design, one of a set of predictions about the nascent market.
Rambus CEO calls for collaboration and an architectural focus for memory
Dr Ron Black also discussed his experiences with the Internet of Things in a lively keynote at the GSA Memory+ Conference in Taipei
DATE: ARM proposes ‘unit of compute’ as basis for energy-efficient systems
ARM CPU chief proposes 'unit of compute' as building block for energy-efficient computation systems
Ambipolar FETs are an each-way bet
Ambipolar FETs, which can be n or p-type dependent on a control gate, could offer a new way to design circuits at 20nm and below.
A first look at CDN Live Silicon Valley
The CDN Live series of Cadence Design Systems user conferences begins with its Silicon Valley edition at San Jose's Doubletree Hotel on March 12-13.
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