IP

January 10, 2020

MRAM pushes speed and endurance at IEDM

IEDM late last year showed how MRAM is being prepared for both FD-SOI and advanced finFET nodes.
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January 7, 2020

Siemens and Arm combine to extend digital twin further into SoC design

Partnership combines Siemens PAVE 360 digital twin with ARM IP, including dedicated automotive offerings, to speed and streamline design toward Level 5.
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December 16, 2019

Mentor delivers eMRAM test for ARM/Samsung FDSOI at 28nm

Tessent test suite targets automotive, AI and IoT projects that need embedded non-volatile memory.
December 11, 2019

Support for RISC-V expands at summit

This week’s RISC-V Summit in California has seen an expansion to the open-source portfolio being built around the architecture as well as increased support from software vendors such as Wind River.
December 10, 2019

Breker adds automated system integration test generation for RISC-V

App joins Portable Stimulus specialist's Trek5 family to reduce manual test writing during verification on designs for the fast-growing RISC-V open-source processor.
December 3, 2019

Imagination splits GPU lanes for high-utilization acceleration

Imagination Technologies has launched a new generation of GPU IP aimed at multitasking compute acceleration.
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October 29, 2019

Foundries call off patent war

GlobalFoundries and TSMC have called off their legal battle with a wide-ranging patent cross-licensing deal.
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October 14, 2019

DVCon Europe looks to software for next phase in verification

October's DVCon Europe conference will have an increased focus on the role of software in electronic systems and the challenges it poses to verification.
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October 8, 2019

Arm to let customers bolt instructions onto V8 processors

Arm has relented on its opposition to custom instructions with the decision to let customers add them to V8-M processors.
October 8, 2019

UltraSoC adds security checks to bus monitoring IP

UltraSoC has developed a bus monitor that will terminate transactions if it detects behavior that breaks rules set by a system designer.
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