Imperas has put together a suite of tools to verify that custom RISC-V processor cores remain compatible with the common infrastructure behind the open-source instruction set.
DAC 2021 is looming and here is our first round up of a major EDA player's plans for the physical event in San Francisco.
University of Florida researcher proposes third-party checks on chiplets to demonstrate they are free of trojans.
A £6.5m grant will fund the development of memories and other IP to improve the control of qubits in quantum computers.
Cloud computing is gaining ground in EDA but close to a third of organizations are planning to stay with on-premises computing for the foreseeable future, according to a survey commissioned by IC Manage.
Sondrel has combined EDA tools with custom SystemC and Python code to develop a system that can help automate the detailed performance analysis of high-level architectures before RTL is generated.
Agile Analog has moved into the supply of cores for detecting hardware-hacking attempts as well as more conventional data-conversion modules.
Emulation capacity and its scalability is a major issue for large SoC designs, said panelists at DVCon Europe.
In a panel at this week’s DVCon Europe, experts described a number of issues facing teams looking to incorporate machine learning in logic verification flows and why some of those efforts will not pay off while others succeed.
Arm’s SystemReady program has revealed a number of the subtleties involved when trying to maintain software compatibility with operating systems without moving to the straightjacket of platforms like those used for the x86-based PC.
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