IP

April 24, 2019

May meeting to push for UVM analog extensions

Accellera is trying to standardize extensions to UVM for mixed-signal design.
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April 22, 2019

Machine learning and chiplets headline VLSI Symposia

Large-scale MCMs and novel device architectures bookend the papers on machine learning at VLSI Symposia in an event that will also cover chiplet integration and other topics.
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April 12, 2019

DesignWare gets automotive boost with GLOBALFOUNDRIES 22FDX SOI qualification

Synopsys and GLOBALFOUNDRIES are developing a portfolio of automotive IP for the chipmakerā€™s 22nm fully depleted silicon-on-insulator (22FDX) process.
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April 2, 2019

Catapult HLS integrates eFPGA IP for faster development

Menta eFPGA IP is highly configurable making it well suited to the evolving designs that exploit HLS abstraction.
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March 26, 2019

DVCon Europe looks to software in call for papers

DVCon Europe has added embedded software, digital twin, machine learning, and RISC-V to the topics the conference organizers want to cover.
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March 20, 2019

Microsoft offers free RTL for fast server compression

Not only has Microsoft decided to make a compression algorithm intended for data centers open source, the company the company is providing its own RTL to anyone who wants to implement it in silicon.
March 18, 2019

PCI may provide key to OCP chiplet standard

The ODSA Workgroup formed by Netronome and others is looking to adopt the PIPE standard for interconnecting chiplets as it starts work on a proof-of-concept module.
March 15, 2019

ES Design West registration opens

Registration has opened for the first ES Design West exhibition, which takes place alongside Semicon West in San Francisco in July.
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March 12, 2019

Free registration opens for DAC

The Design Automation Conference (DAC) has kicked off free registration for the exhibit floor at early June's Las Vegas event.
March 11, 2019

China Focus 3: The R&D template

5G has given Beijing a development template to use across its Made in China 2025 program.
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