Andes and SiFive attempt to lower the barriers to entry for SoC designs based on RISC-V processor cores.
IoT ecosystems should shift from WiFi to cellular connectivity to make them easier to secure and manage.
White paper goes from general principles through to worked examples of efficient machine-learning algorithm implmentations on dedicated processor IP.
Microsoft Azure aims to use royalty-free IP to build a more secure IoT and extend the reach of its cloud services.
Developing a security assurance standard for IP faces numerous problems but Accellera working-group members are trying to find an answer.
Cadence has developed a version of its Protium prototyping engine that supports larger designs and which is intended to go into data-center racks.
Achronix is introducing an FPGA architecture that pulls a full network-on-chip into the programmable-logic fabric combined with hardened matrix-math processors for AI.
Mentor is active across the program and its main and Verification Academy booths within the exhibition in Las Vegas.
EDA and IP supporters of the new event see the goal of greater integration with the electronic systems supply chain as fundamental to their involvement.
Accellera is trying to standardize extensions to UVM for mixed-signal design.
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