IP

Alphawave Semi has collaborated with Arm on the development of an advanced compute chiplet based on Arm’s Neoverse compute subsystems.

Imec has developed cleaner techniques for preparing die-to-wafer bonding components for high-density logic-memory stacks and optical integration.

The upcoming VLSI Symposium will examine progress in using backside contacts and 3D structures to improve density and speed as well as continuing improvements to finFET processes.

Arm has launched what the company claims is its highest-performance and most-efficient AI accelerator.

Certification to ISO 26262 for automotive systems and compatibility with the latest Arm9 generation of processors and the CHI-E interface are among the updates to Arteris’ Ncore cache-coherent on-chip network IP framework.

Arm is working with Cadence and Siemens on separate projects to support its plans in the SDV space.

Cadence has agreed to work with Intel Foundry Services on IP and flows for the 18A process, which will include backside power delivery and nanosheet transistors.

The two best papers at the recent DVCon Europe underlined two of the issues that now face chip-implementation teams: efficient flows and reliability.

Shifting to low-carbon generation for electricity would do much to cut the carbon footprint of semiconductor processes according to work shown at this year’s IEDM.

Applied Materials and CEA-Leti have expanded their collaboration with the creation of a joint lab to develop materials useful for sensors, RF communications, and power devices, and with a focus on heterogeneous integration.