Siemens EDA has become the first of the major EDA vendors to join the DARPA Toolbox Initiative.
Cadence has organized its machine-learning platforms into three families intended to cover a wide range of on-device AI applications.
Arm and flexible-electronics specialist PragmatIC have demonstrated a 32bit processor implemented on a plastic substrate.
Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.
The added complexity of managing reliability as chiplet-based designs become more common will need to be managed using digital-twin techniques, says a professor working in the field.
Accellera has approved version 1.0 of the SA-EDI standard, intended to provide a consistent way of describing security concerns for IP cores.
Xilinx has reworked its Versal FPGA for edge-AI applications.
TSMC will provide three different standard-cell libraries for its upcoming finFET-based 3nm process to cover requirements from high-density mobile to high-performance computing, allowing tradeoffs for area and circuit frequency.
Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
Arm is reworking the DesignStart scheme it introduced several years, moving it under the umbrella of the broader Flexible Access program.
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