IP

June 23, 2020

Mentor to bring SoC debug and instrumentation into the portfolio

Siemens has agreed to acquire UK-based debug and on-chip instrumentation startup UltraSoC and will fold the operation into Mentor’s Tessent test-software product line.
Article  |  Tags: , , , , ,   |  Organizations: ,
June 10, 2020

Onchip sensors aim for finer-granularity heat measurements

Moortec has reworked its thermal-sensing core design to allow for finer-grained use on SoCs being designed for the 5nm node.
Article  |  Tags: , , ,   |  Organizations:
May 26, 2020

DVCon 2020 to repeat sessions online

DVCon US is to repeat sessions online from today until the middle of August, with exclusive access to registered attendees through early June.
Article  |  Tags: ,   |  Organizations:
May 14, 2020

The price of reliability is constant vigilance

Papers presented at the recent IRPS conference showed the growing importance of lifetime monitoring to the problem of handling components as they age.
Article  |  Tags: , , , ,   |  Organizations: , ,
April 29, 2020

Arm extends free access to core designs for startups

Arm has put together a program based on its existing Flexible Access model that is intended to provide early-state startups with a broader list of cores they can prototype before needing to take out a full licence.
Article  |  Tags: , , , , ,   |  Organizations:
April 16, 2020

IP partnership aims to crack down on physical hacks

UltraSoC and Agile Analog have teamed up to build an infrastructure that can help guard against physical attacks on SoCs.
Article  |  Tags: , , ,   |  Organizations: ,
March 4, 2020

CEVA splits vectors for more efficient 5G

CEVA has reworked its XC architecture to provide what the company claims is the kind of performance boost needed to handle phase-two 5G applications once Release 17 rolls out.
Article  |  Tags: , , , ,   |  Organizations:
February 24, 2020

DVCon US 2020 preview: SmartDV

The latest in MIPI and DDR design and verification IP as well as protocol debug are highlights in SmartDV's DVCon program.
Article  |  Tags: , , , , , , ,   |  Organizations: ,
February 14, 2020

Debug connects with manufacturing test to cut product recall costs

UltraSoC has kicked off a collaboration with PDF Solutions to build a system better able to use runtime information to identify devices that are likely to fail in the field and so reduce the impact of product recalls.
Article  |  Tags: , ,   |  Organizations: ,
February 10, 2020

Arm adds AI to Cortex-M cores

Arm has launched a pair of cores intended to bring acceleration for machine learning to its Cortex-M series of processors.
Article  |  Tags: , ,   |  Organizations:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors