Imperas and Synopsys team on RISC-V debug
Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
IP
Accellera forms CDC working group and takes security standard to IEEE
Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
DVCon Europe best paper speeds up memory-controller tests
The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circuits.
RISC-V gets verification and security IP additions
Ahead of the RISC-V Summit in San Jose, Imperas Software has issued updates to its ImperasDV verification IP for RISC-V verification and Codasip has launched a secure-processor initiative.
Imec pushes endurance on ferro memory at IEDM
Imec has developed a high-endurance ferroelectric capacitor that could form the basis of storag-class embedded and standalone memories.
Semiwise brings cryogenic models to SOI
Semiwise has developed transistor models for the GlobalFoundries 22FDX that cover operation at cryogenic temperatures.
Nvidia proposes split-level link for chiplet interconnect
Nvidia revealed at its Fall GTC work the company has done on a bidirectional energy-saving chiplet interconnect that could hit the equivalent of 50Gbit/s per line.
Agile Analog adds digital library for easier porting
Agile Analog has launched its own digital standard cell library, designed to be used in the control circuits for analog blocks that form the IP company’s main offering.
Intel and partners join for RISC-V development push
Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
Imperas releases RISC-V coverage library as open source
Imperas Software has published an open-source functional-coverage library for RISC-V cores.
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