IP

March 4, 2020

CEVA splits vectors for more efficient 5G

CEVA has reworked its XC architecture to provide what the company claims is the kind of performance boost needed to handle phase-two 5G applications once Release 17 rolls out.
Article  |  Tags: , , , ,   |  Organizations:
February 24, 2020

DVCon US 2020 preview: SmartDV

The latest in MIPI and DDR design and verification IP as well as protocol debug are highlights in SmartDV's DVCon program.
Article  |  Tags: , , , , , , ,   |  Organizations: ,
February 14, 2020

Debug connects with manufacturing test to cut product recall costs

UltraSoC has kicked off a collaboration with PDF Solutions to build a system better able to use runtime information to identify devices that are likely to fail in the field and so reduce the impact of product recalls.
Article  |  Tags: , ,   |  Organizations: ,
February 10, 2020

Arm adds AI to Cortex-M cores

Arm has launched a pair of cores intended to bring acceleration for machine learning to its Cortex-M series of processors.
Article  |  Tags: , ,   |  Organizations:
January 24, 2020

SureCore provides 30-day test for SRAM compiler

SureCore has started running 30-day trials of its low-power memory compiler.
Article  |  Tags: , , , ,   |  Organizations:
January 10, 2020

MRAM pushes speed and endurance at IEDM

IEDM late last year showed how MRAM is being prepared for both FD-SOI and advanced finFET nodes.
Article  |  Tags: , , ,   |  Organizations: , , ,
January 7, 2020

Siemens and Arm combine to extend digital twin further into SoC design

Partnership combines Siemens PAVE 360 digital twin with ARM IP, including dedicated automotive offerings, to speed and streamline design toward Level 5.
Article  |  Tags: , , , ,   |  Organizations: , ,
December 16, 2019

Mentor delivers eMRAM test for ARM/Samsung FDSOI at 28nm

Tessent test suite targets automotive, AI and IoT projects that need embedded non-volatile memory.
December 11, 2019

Support for RISC-V expands at summit

This week’s RISC-V Summit in California has seen an expansion to the open-source portfolio being built around the architecture as well as increased support from software vendors such as Wind River.
December 10, 2019

Breker adds automated system integration test generation for RISC-V

App joins Portable Stimulus specialist's Trek5 family to reduce manual test writing during verification on designs for the fast-growing RISC-V open-source processor.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors