The upcoming VLSI Symposia will feature a number of papers that show the ways in which novel approaches are going to be needed to continue scaling.
The Linley Spring Conference saw several vendors present architectures that they claim can deliver more performance to edge systems than what are now traditional approaches.
Siemens's expansion of the Veloce hardware-assisted verification platform delivers on one of its current mission statements.
EDA's lower profile during the US-China semiconductor face-off could be coming to an end.
The formal apps start-up has built strong positions in automotive and RISC-V and will strengthen Siemens in competition with Cadence.
The Accellera board has approved version 2.0 of the Portable Test and Stimulus Standard.
The vendor has reworked its website and discussed more about its strategy going forward, following its rebranding from Mentor.
Accellera has published the version 1.0 draft of the proposed Security Annotation for Electronic Design Integration standard.
Siemens has introduced a cloud-based DFM tool intended to bridge the gap between the electronics design and manufacturing.
Cadence Design Systems has designed a new custom processor for the Z2 emulator and employed Xiliinx UltraScale+ for the prototyping platform.
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