Blog Topics

July 28, 2021

Automate latchup verification for 3DIC

A Siemens white paper describes a way of automatically deriving information from 2.5D/3DIC designs to streamline latchup design-rules verification.
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July 27, 2021

ST makes its first 200mm SiC wafers

STMicroelectronics has made its first silicon carbide wafers that can be run on a 200mm line.
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July 22, 2021

Cadence uses reinforcement learning to tune flow

Cadence has launched a tool that the company claims can speed up implementation by applying machine learning across the flow.
July 22, 2021

Arm shows off biggest flex processor so far

Arm and flexible-electronics specialist PragmatIC have demonstrated a 32bit processor implemented on a plastic substrate.
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July 19, 2021

Chiplet design raises big questions

Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.
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July 16, 2021

How to meet formal embedded software guidance for medical devices

Vulnerabilities in connected healthcare products have led medical requlators to issue further security recommendations for their design and maintenance.
July 15, 2021

Chiplets to need digital twins for reliability

The added complexity of managing reliability as chiplet-based designs become more common will need to be managed using digital-twin techniques, says a professor working in the field.
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July 14, 2021

Accellera approves IP security-documentation standard

Accellera has approved version 1.0 of the SA-EDI standard, intended to provide a consistent way of describing security concerns for IP cores.
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June 21, 2021

From iterative to in-design DRC and debug for place and route

Learn how Calibre RealTime Digital allows you to identify, explore and fix DRC violations as you go.
June 17, 2021

Standard arrives for thermal simulation data

A de facto standard for exchanging thermal information about designs has become JEDEC standard JEP181.

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