Blog Topics

January 10, 2020

MRAM pushes speed and endurance at IEDM

IEDM late last year showed how MRAM is being prepared for both FD-SOI and advanced finFET nodes.
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January 7, 2020

Siemens and Arm combine to extend digital twin further into SoC design

Partnership combines Siemens PAVE 360 digital twin with ARM IP, including dedicated automotive offerings, to speed and streamline design toward Level 5.
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December 18, 2019

On-demand DRC within P&R cuts closure time in half for MaxLinear

Case study describes how RF/AMS specialist used Calibre RealTime Digital within its flow for a high-end DSP SoC.
December 18, 2019

Capacitive link to power cheap wireless tags

Imec, TNO, and Cartamundi have developed a low-cost way of letting tags communicate with embedded devices wirelessly by using a capacitive touchscreen.
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December 17, 2019

Automating the pain out of clock domain crossing verification

A new CDC methodology uses automation and data hooks to improve a notoriously lengthy and tricky task - verifying synchronizers.
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December 16, 2019

Mentor delivers eMRAM test for ARM/Samsung FDSOI at 28nm

Tessent test suite targets automotive, AI and IoT projects that need embedded non-volatile memory.
December 11, 2019

Support for RISC-V expands at summit

This week’s RISC-V Summit in California has seen an expansion to the open-source portfolio being built around the architecture as well as increased support from software vendors such as Wind River.
December 10, 2019

Breker adds automated system integration test generation for RISC-V

App joins Portable Stimulus specialist's Trek5 family to reduce manual test writing during verification on designs for the fast-growing RISC-V open-source processor.
December 4, 2019

Cadence to acquire AWR from National Instruments

Cadence Design Systems has agreed to buy the AWR RF-design company from its current owner National Instruments for approximately $160m.
December 3, 2019

Imagination splits GPU lanes for high-utilization acceleration

Imagination Technologies has launched a new generation of GPU IP aimed at multitasking compute acceleration.
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