A Siemens white paper describes a way of automatically deriving information from 2.5D/3DIC designs to streamline latchup design-rules verification.
STMicroelectronics has made its first silicon carbide wafers that can be run on a 200mm line.
Cadence has launched a tool that the company claims can speed up implementation by applying machine learning across the flow.
Arm and flexible-electronics specialist PragmatIC have demonstrated a 32bit processor implemented on a plastic substrate.
Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.
Vulnerabilities in connected healthcare products have led medical requlators to issue further security recommendations for their design and maintenance.
The added complexity of managing reliability as chiplet-based designs become more common will need to be managed using digital-twin techniques, says a professor working in the field.
Accellera has approved version 1.0 of the SA-EDI standard, intended to provide a consistent way of describing security concerns for IP cores.
Learn how Calibre RealTime Digital allows you to identify, explore and fix DRC violations as you go.
A de facto standard for exchanging thermal information about designs has become JEDEC standard JEP181.
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