AI

May 30, 2023

Charting the path for machine learning in functional verification

A comprehensive review of ML's potential and its current use identifies challenges ahead.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
December 1, 2022

Identifying AI opportunities in PCB design

The key to exploiting AI is being clear about where its family of technologies can help to improve and democratize design.
November 23, 2022

Chipletz pushes packaging design for AI, HPC and immersive use-cases

The Austin-based start-up used Siemens EDA software to deploy a cutting-edge Smart Substrate based on advanced packaging technology.
July 12, 2022

Devgan plans for optimization through machine learning

Cadence president expects expanded role for reinforcement learning in tool portfolio and looks for help on AI for verification.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
June 28, 2022

Coherency verification for CXL

CXL is a strongly-backed technology aimed at improving connectivity across datacenters handling high demand HPC and AI applications.
October 7, 2021

Combined database underpins 3DIC design suite

Cadence has built a unified database to support a group of tools to support the planning and implementation of 3DIC designs.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,   |  Organizations:
August 5, 2021

Keynotes for DVCon Europe announced

DVCon Europe has announced its first two keynote speakers, who will cover the topics of AI and the role of virtualisation in ADAS design and implementation
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
May 28, 2021

PCIe 6.0 gets verification IP as formal arrival approaches

Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
Article  |  Topics: Blog - EDA, IP, - Verification  |  Tags: , , , , , , ,   |  Organizations: ,
December 18, 2020

Virtual emulation delivers verification for the latest storage devices

Computational storage devices are posing a new raft of challenges that is being addressed using a powerful pre-silicon methodology.
November 3, 2020

Tessent Streaming Scan Network to shrink SoC test writing and runtimes

Mentor's latest additions to Tessent aim to cut test time by a factor of four but remains tailored for increasing design complexity.
Article  |  Topics: Blog Topics  |  Tags: , , , , ,   |  Organizations: , ,

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