Xilinx aims for software flow with Vitis
Xilinx has released the first version of its Vitis development environment as the company aims to capture a user base that is more used to software than hardware tools.
AI
IEDM homes in on connected devices
The IEDM has chosen a theme based around technologies for connected devices for its upcoming conference in December.
EDA with ‘AI inside’ – Mentor’s Joe Sawicki offers an insider’s view
Mentor has a host of tools - some public, some not - that leverage AI and ML. EVP Joe Sawicki has been describing the strategy behind their development.
Making the case for HLS in autonomous drive
The automotive market faces challenges that make it a prime candidate for the greater use of high-level synthesis on designs with AI and ML content.
Roadmapping the quantum realm
The US Quantum Economic Development Consortium is looking to stimulate a supply chain and technology infrastructure for quantum computing, with more about its efforts due to come out in the next few days.
Verifying in an HLS context for AI and ML designs
A SystemC/C++ app from a library that extends the OneSpin 360 DV-Verify platform was used by ML IP specialist NanoSemi on a 5G/WiFi project.
Building an ecosystem around HLS for AI and ML designs
Mentor's AI Accelerator Ecosystem adds reference designs, libraries and other forms of support around its Catapult HLS platform.
AI and ML fuel Catapult and Calibre updates
Mentor takes the wraps off new machine learning fueled features in its HLS and physical design families ahead of DAC 2019.
Boost your DFT efficiency for AI silicon design
Three hierarchical DFT strategies help cut time-to-market for large AI chips by exploiting regularity and addressing test at the RTL.
Catapult HLS integrates eFPGA IP for faster development
Menta eFPGA IP is highly configurable making it well suited to the evolving designs that exploit HLS abstraction.
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