Mentor takes the wraps off new machine learning fueled features in its HLS and physical design families ahead of DAC 2019.
Three hierarchical DFT strategies help cut time-to-market for large AI chips by exploiting regularity and addressing test at the RTL.
Menta eFPGA IP is highly configurable making it well suited to the evolving designs that exploit HLS abstraction.
Do China's ambitions as a world-class innovator face fundamental challenges as a result of the sector's existing economic infrastructure?
DVCon USA is coming soon. Mentor's 2019 involvement includes a keynote from parent Siemens and a tutorial on managing your formal verification processes.
A recent white paper from Synopsys outlines the complexities of developing hardware for use in machine-learning and artificial-intelligence (AI) systems.
Mentor has added three companies since its acquisition a little over a year ago - and there's method to this buying spree.
Machine learning is gradually moving into implementation and verification tools for EDA.
For nVidia chief scientist and Stanford professor Bill Dally, now is a great time to be involved in hardware design, thanks to the rise of AI.
Synopsys applies AI to speed PrimeTIme, as part of wider strategy to exploit machine learning to ease chip design
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