AI

April 16, 2019

Boost your DFT efficiency for AI silicon design

Three hierarchical DFT strategies help cut time-to-market for large AI chips by exploiting regularity and addressing test at the RTL.
Article  |  Topics: Blog Topics, Tested Component to System  |  Tags: , , , , , ,   |  Organizations:
April 2, 2019

Catapult HLS integrates eFPGA IP for faster development

Menta eFPGA IP is highly configurable making it well suited to the evolving designs that exploit HLS abstraction.
Article  |  Topics: Blog - EDA, - HLS, Blog - IP  |  Tags: , , , , ,   |  Organizations: ,
February 25, 2019

China Focus 2: The Design Dilemma

Do China's ambitions as a world-class innovator face fundamental challenges as a result of the sector's existing economic infrastructure?
February 11, 2019

DVCon USA 2019 preview: Mentor

DVCon USA is coming soon. Mentor's 2019 involvement includes a keynote from parent Siemens and a tutorial on managing your formal verification processes.
October 2, 2018

White paper outlines challenges of developing machine-learning hardware

A recent white paper from Synopsys outlines the complexities of developing hardware for use in machine-learning and artificial-intelligence (AI) systems.
Article  |  Topics: Blog Topics  |  Tags: , , ,   |  Organizations:
August 1, 2018

Mentor as a maturing Siemens business: 1. Acquisitions

Mentor has added three companies since its acquisition a little over a year ago - and there's method to this buying spree.
June 26, 2018

EDA learns to love AI

Machine learning is gradually moving into implementation and verification tools for EDA.
June 21, 2018

AI is all about low-energy hardware says Dally

For nVidia chief scientist and Stanford professor Bill Dally, now is a great time to be involved in hardware design, thanks to the rise of AI.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , , , ,   |  Organizations: ,
June 6, 2018

Synopsys speeds PrimeTime with AI

Synopsys applies AI to speed PrimeTIme, as part of wider strategy to exploit machine learning to ease chip design
Article  |  Topics: Blog - EDA, - Verification  |  Tags: ,   |  Organizations: ,
May 22, 2018

IEDM 2018 aims to span quantum, neuromorphic and CMOS devices

IEDM has issued a call for papers for its 2018 conference, expecting to cover devices and circuit interactions in neuromorphic, quantum and conventional computing.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations:

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