Expert Insights

Tom Anderson  |  August 19, 2019

Take advantage of the automated refactoring of design and verification code

Refactoring saves time and resuources by converting code to a common format and eliminates redundancies to make it more readable and maintainable.
Ron Press  |  August 15, 2019

Achieving more efficient hierarchical DFT for Arm subsystems

Hierarchical DFT for Arm-based SoCs is easier than ever with the arrival of a complete reference flow from Mentor and Arm.
Topics: EDA - DFT, - EDA Topics  |  Tags: ,   |  Organizations: ,   |  
Ashish Darbari  |  August 9, 2019

Spreading the word on formal in Bangalore

Doc Formal rounds up some of the the key observations about verfication made during July’s Synopsys VC Formal SIG event in India.
Puneet Sinha  |  July 24, 2019

Overcoming systemic design challenges for electric vehicles

EV design requires an ability to address interrelated tasks in areas such as architecture, performance, lifetime, range and charging speed.
Tom Anderson  |  July 23, 2019

Correct design and verification coding errors as you type

An IDE designed to catch typographical errors, missing declarations and inconsistent references in your code can hugely reduce your time in debug.
Topics: EDA - IC Implementation, Verification  |  Tags: , , , , , , , , , ,   |  Organizations:   |  
Ashish Darbari  |  July 4, 2019

A new formal proof kit for RISC-V processors

Doc Formal describes a strategy developed by his company Axiomise to apply formal verification proofs to open-source processor for safety, security and reliability.
Paul Dempsey  |  June 18, 2019

The vocal persuader

In conversation with author and SEMICON West/ES Design West keynoter Bob Pearson on the challenges facing tech on external and internal communication.
Tom Anderson  |  June 18, 2019

A helping hand for design and verification

Integrated design environments and features within them such as auto-complete deliver valuable efficiencies for input, verification and debut.
Topics: Uncategorized  |  Tags: , , ,   |  Organizations:   |  
Dennis Joseph  |  June 11, 2019

Speed up design and verification with a smaller layout

How to remove or extract portions of a layout for easier, more focused and faster project delivery.
Topics: EDA - IC Implementation, Verification  |  Tags: , , , ,   |  Organizations:   |  
Tom Anderson  |  May 15, 2019

Why hyperlinks are essential for HDL debugging

Text editors have major debug limitations that the use of hyperlinks in integrated development environments help you overcome.
Topics: EDA - IC Implementation, Verification  |  Tags: , , , ,   |  Organizations:   |  

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