Expert Insights

Paul Dempsey  |  October 16, 2019

Achieving the interactive development of low-power designs

Power intent files have increased efficiency and the use of an IDE can prevent them becoming outdated as a design evolves.
Topics: EDA - IC Implementation, Verification  |  Tags: , , , , , , , , , ,   |  Organizations:   |  
Dina Medhat  |  October 9, 2019

An easier way to make reliability rules and checks more consistent

Learn how XML-based constraints can standardize rule development and use with coding examples for the Calibre PERC reliability platform.
Richard Pugh  |  October 7, 2019

Emulation makes it possible to stay on the road to autonomous vehicles

Autonomous vehicle functional verification needs to prove the predictable behavior, safety and security of complex SoCs and their associated software, sensors and actuators, demanding greater use of hardware emulation.
Topics: Digital Twin, EDA - Verification  |  Tags: ,   |  Organizations:   |  
Tom Anderson  |  September 25, 2019

Delivering on the advanced refactoring of design and verification code

An IDE is critical to top quality refactoring. Here are some tips and examples of how to achieve that.
Topics: Uncategorized  |  Tags: , , , , , , , , ,   |  Organizations: ,   |  
Hossam Sarhan  |  September 19, 2019

Today’s analog/RF designs need interconnect inductance extraction

Parasitic extraction has to take more account of inductive effects as operating frequencies rise and feature sizes shrink in complex SoCs.
Topics: Electrical Design, EDA - IC Implementation  |  Tags: ,   |  Organizations: ,   |  
John Blyler  |  September 13, 2019

AI firsts (and more) at America’s SEMICON

SEMICON West showed a distinct thematic shift away from preserving Moore's Law to assessing the architectural implications of AI, as EDA was brought into the event.
Adnan Hamid  |  September 10, 2019

Using portable stimulus for automotive random error analysis

The Portable Stimulus Standard helps overcome many of the verification challenges inherent in the strict requirements of ISO 26262.
Tom Anderson  |  August 19, 2019

Take advantage of the automated refactoring of design and verification code

Refactoring saves time and resuources by converting code to a common format and eliminates redundancies to make it more readable and maintainable.
Ron Press  |  August 15, 2019

Achieving more efficient hierarchical DFT for Arm subsystems

Hierarchical DFT for Arm-based SoCs is easier than ever with the arrival of a complete reference flow from Mentor and Arm.
Topics: EDA - DFT, - EDA Topics  |  Tags: ,   |  Organizations: ,   |  
Ashish Darbari  |  August 9, 2019

Spreading the word on formal in Bangalore

Doc Formal rounds up some of the the key observations about verfication made during July’s Synopsys VC Formal SIG event in India.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors