Expert Insights - EDA

Sherif Hany  |  October 21, 2021

Advanced symmetry verification is a thing of beauty

Innovation is extending the technique's power across areas such as context-aware layout, accounting for multi-patterning and implementing fill.
Swathi Rangarajan  |  September 13, 2021

Hit your tapeout schedules with in-design signoff DRC

Delivering physical implementations at new process nodes is getting ever harder. Learn how to stay on track by checking work is rule-compliant as you go.
Tina Durgia  |  June 25, 2021

Use machine learning and visualization to accelerate Liberty file verification

Learn how to bring together your NLDM and CCS models to reach timing closure faster with Solido Analytics.
Srinivas Velivala  |  May 31, 2021

How you can decide what level of DRC you need when you need it

Using on-demand rule checks during place-and-route boosts efficiency and design quality.
Chris Edwards  |  April 29, 2021

DVCon Europe best paper assesses clock design

The best paper at DVCon Europe 2020 analyzed different multiclock strategies for SoCs for their power and flexibility
Topics: EDA - IC Implementation  |  Tags: , , , ,   |  Organizations:   |  
Paul Dempsey  |  April 6, 2021

The path to full functional monitoring

Joe Sawicki of Siemens EDA recently addressed the main trends in design delivery from architecture to validation to digital twins - and where they may soon take the industry and its products.
Alieen Ryan  |  March 22, 2021

Silicon lifecycle solutions help you listen to your chip

SLS brings the power of product lifecycle management to the increasingly complex oversight challenges in electronic systems design.
Tom Anderson  |  December 10, 2020

e language users deserve IDE support too

With features that keep it in current use such as aspect-oriented programming, the e language can leverage integrated design environments. Learn how.
Dina Medhat  |  October 16, 2020

Not using reliability check waivers? You’re wasting valuable time

Reliability rule checks need - and now get - more granular analysis that allows designers to adopt proposed waivers with much greater confidence.
Topics: EDA - DFM  |  Tags: , , , , , ,   |  Organizations:   |  
Tom Anderson  |  September 25, 2020

Extract benefit from the automated refactoring of VHDL code

VHDL has come a long way in terms of complexity. An integrated development environment helps you deliver better and more compliant code quickly.

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