Expert Insights - EDA

Lauro Rizzatti  |  February 28, 2023

Shift left to tackle key O-RAN verification challenges

O-RAN compatible Radio Unit (O-RU) and Distributed Unit (O-DU) verification no longer needs to wait until the post-silicon stage.
Topics: EDA Topics, EDA - Verification  |  Tags: , , , , ,   |  
Nebabie Kebebew  |  February 8, 2023

How to migrate SoC design to the cloud

Moving part of all of a design flow to the cloud involves careful preparation and evaluation as there is no 'one-size-fits-all'.
Keith Felton  |  January 26, 2023

Give the people what they want: toward making 3D IC mainstream

Learn more about the five interconnected workflows that are democratizing next generation design in the emerging chiplet age.
Hossam Sarhan  |  December 23, 2022

Reliability verification simplified for multi-power domain designs

Automating reliability verification with tools that offer packaged checks provides greater consistency and accuracy across an increasingly complex process.
SEMICON West special report  |  October 17, 2022

Rising to the verification challenge of open source

Fast emerging options, like RISC-V, could foster massive growth in design but verification still needs commercial tools, a Semicon West panel found.
Dhruv Garg  |  September 7, 2022

NVMe-oF – The future of cloud storage

NVMe over Fabrics (NVMe-oF) extends the memory standard for burgeoning data traffic and the demands of AI and machine learning.
Jeff Hancock  |  September 6, 2022

Keeping up with rapid innovation in cockpit domain controllers

Automotive cockpit design is being driven forward by prevailing trends in the wider market.
James Paris  |  April 28, 2022

Layout customization improves productivity in design and verification flows

What are the options and how do you balance overarching CAD requirements and personal preferences?
Wu Yang  |  April 25, 2022

Toward usable and scalable DFT for 3D IC design

Both 3D IC and 2.5D IC techniques are being used on more designs and the DFT infrastructure is evolving to meet the challenges they pose.
Topics: EDA - DFT  |  Tags:   |  Organizations:   |  
Tom Anderson  |  March 21, 2022

Executable specifications boost SoC and IP efficiency

Automating executable specifications as they evolve can deliver major efficiencies.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors