Expert Insights - EDA

Tom Anderson  |  August 19, 2019

Take advantage of the automated refactoring of design and verification code

Refactoring saves time and resuources by converting code to a common format and eliminates redundancies to make it more readable and maintainable.
Ron Press  |  August 15, 2019

Achieving more efficient hierarchical DFT for Arm subsystems

Hierarchical DFT for Arm-based SoCs is easier than ever with the arrival of a complete reference flow from Mentor and Arm.
Topics: EDA - DFT, - EDA Topics  |  Tags: ,   |  Organizations: ,   |  
Ashish Darbari  |  August 9, 2019

Spreading the word on formal in Bangalore

Doc Formal rounds up some of the the key observations about verfication made during July’s Synopsys VC Formal SIG event in India.
Tom Anderson  |  July 23, 2019

Correct design and verification coding errors as you type

An IDE designed to catch typographical errors, missing declarations and inconsistent references in your code can hugely reduce your time in debug.
Topics: EDA - IC Implementation, Verification  |  Tags: , , , , , , , , , ,   |  Organizations:   |  
Ashish Darbari  |  July 4, 2019

A new formal proof kit for RISC-V processors

Doc Formal describes a strategy developed by his company Axiomise to apply formal verification proofs to open-source processor for safety, security and reliability.
Dennis Joseph  |  June 11, 2019

Speed up design and verification with a smaller layout

How to remove or extract portions of a layout for easier, more focused and faster project delivery.
Topics: EDA - IC Implementation, Verification  |  Tags: , , , ,   |  Organizations:   |  
Tom Anderson  |  May 15, 2019

Why hyperlinks are essential for HDL debugging

Text editors have major debug limitations that the use of hyperlinks in integrated development environments help you overcome.
Topics: EDA - IC Implementation, Verification  |  Tags: , , , ,   |  Organizations:   |  
Lauro Rizzatti and Gabriele Pulini  |  May 14, 2019

How emulation’s virtual mode boosts productivity: Part Two

Part two of this feature describes three use-cases that exploit the VirtuaLAB technology in HDMI, PCIe and Ethernet designs.
Topics: EDA - DFT, Verification  |  Tags: , , ,   |  Organizations:   |  
Lauro Rizzatti and Gabriele Pulini  |  May 1, 2019

How emulation’s virtual mode boosts productivity: Part One

This two-part article describes advantages when using a hardware emulation platform in virtual mode compared with in-circuit-emulation.
Topics: EDA - DFT, Verification  |  Tags: , , ,   |  Organizations: ,   |  
Paul Dempsey  |  April 2, 2019

High-level synthesis for AI: Part Two

How Chips&Media used HLS on the development of a computer vision IP block.

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