Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.
As the project that funded OpenRoad draws to a close, experts pondered its wider future at the 59th DAC.
CXL is a strongly-backed technology aimed at improving connectivity across datacenters handling high demand HPC and AI applications.
Intel expects to double logic density through metal scaling and smaller cells with upcoming process.
Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.
The upcoming VLSI Symposia will feature a number of papers that show the ways in which novel approaches are going to be needed to continue scaling.
The metal has done sterling service for 20 years but the time is approaching to find a replacement for copper as problems with parasitics continue to build up, work presented at last month’s IEDM shows. But it's not an obvious switch.
Work presented at IEDM 2020 shows taking advantage of the IC backside for power and ground for the additional area can deliver further benefits for IR drop and security.
This year's IEDM will feature papers that exploit stacked nanoribbons to reduce CMOS footprint, graphene interconnects that support easier integration, and the variability prospects of 2D semiconductors.
View All Sponsors