Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
Keynotes at this year’s IRPS conference focused on the way in which scaling is forcing changes to the way that the reliability aspects of semiconductors are examined.
Intel describes active countermeasures for physical attacks at CICC as part of a trend towards more adaptive IoT silicon.
IEDM late last year showed how MRAM is being prepared for both FD-SOI and advanced finFET nodes.
Different forms of heterogeneous integration take center stage at the IEEE International Electron Device Meeting (IEDM) in December this year.
Non-volatile alternatives to flash are finally moving out of the lab as Applied Materials launches production tools and Arm starts pushing MRAM.
ES Design West aims to help integrate the supply chain but also has plenty of engineering content aimed at low power, security, embedded and more.
The US Quantum Economic Development Consortium is looking to stimulate a supply chain and technology infrastructure for quantum computing, with more about its efforts due to come out in the next few days.
Developing a security assurance standard for IP faces numerous problems but Accellera working-group members are trying to find an answer.
The formal specialist is extending its line for Intel FPGAs that target areas such as AI/ML and HPC, and building out a RISC-V suite focused on ISA compliance.
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