Intel

July 19, 2021

Chiplet design raises big questions

Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.
Article  |  Topics: Blog - EDA, IP, PCB  |  Tags: , , , ,   |  Organizations: , , ,
May 2, 2021

Alternative scaling approaches form VLSI 2021 technology highlights

The upcoming VLSI Symposia will feature a number of papers that show the ways in which novel approaches are going to be needed to continue scaling.
January 15, 2021

Copper’s future is troubled but it’s likely to stick around

The metal has done sterling service for 20 years but the time is approaching to find a replacement for copper as problems with parasitics continue to build up, work presented at last month’s IEDM shows. But it's not an obvious switch.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: , , , ,
December 18, 2020

Backside metal defends against IR drop and side-channel attacks

Work presented at IEDM 2020 shows taking advantage of the IC backside for power and ground for the additional area can deliver further benefits for IR drop and security.
November 9, 2020

IEDM 2020 highlights transistor and interconnect advances

This year's IEDM will feature papers that exploit stacked nanoribbons to reduce CMOS footprint, graphene interconnects that support easier integration, and the variability prospects of 2D semiconductors.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: , ,
November 3, 2020

Tessent Streaming Scan Network to shrink SoC test writing and runtimes

Mentor's latest additions to Tessent aim to cut test time by a factor of four but remains tailored for increasing design complexity.
Article  |  Topics: Blog Topics  |  Tags: , , , , ,   |  Organizations: , ,
October 15, 2020

DVCon Europe: using all the tools at your disposal

Among the papers that will be presented at the end of October, this year's DVCon Europe will demonstrate the benefits of taking good ideas from wherever you can in the pursuit of more effective verification flows.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations: , , ,
May 26, 2020

Nanometer scaling puts focus on power at VLSI in June

Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: , , , ,
April 30, 2020

Scaling drives targeted analysis of reliability issues

Keynotes at this year’s IRPS conference focused on the way in which scaling is forcing changes to the way that the reliability aspects of semiconductors are examined.
March 24, 2020

Feed fake news to hardware hackers

Intel describes active countermeasures for physical attacks at CICC as part of a trend towards more adaptive IoT silicon.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:

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