Tessolve is bringing its Verification Futures conference to the US with an event scheduled for mid-September.
Backside power delivery could lead to improvements in chip density and more straightforward place-and-route phases according to work presented at this year’s VLSI Symposium.
Intel Foundry Services has signed a deal with Arm that will see the two companies work on a program of system and design-technology co-optimization.
Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.
As the project that funded OpenRoad draws to a close, experts pondered its wider future at the 59th DAC.
CXL is a strongly-backed technology aimed at improving connectivity across datacenters handling high demand HPC and AI applications.
Intel expects to double logic density through metal scaling and smaller cells with upcoming process.
Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.
The upcoming VLSI Symposia will feature a number of papers that show the ways in which novel approaches are going to be needed to continue scaling.
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