Intel

August 31, 2022

Intel and partners join for RISC-V development push

Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
August 3, 2022

Accellera attempts to standardize CDC data

Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.
Article  |  Topics: Blog Topics, Blog - EDA, IP  |  Tags: , , ,   |  Organizations: ,
July 18, 2022

Open-source EDA grapples with the incentives issue

As the project that funded OpenRoad draws to a close, experts pondered its wider future at the 59th DAC.
June 28, 2022

Coherency verification for CXL

CXL is a strongly-backed technology aimed at improving connectivity across datacenters handling high demand HPC and AI applications.
June 20, 2022

Intel talks 4 at VLSI

Intel expects to double logic density through metal scaling and smaller cells with upcoming process.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
July 19, 2021

Chiplet design raises big questions

Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.
Article  |  Topics: Blog - EDA, IP, PCB  |  Tags: , , , ,   |  Organizations: , , ,
May 2, 2021

Alternative scaling approaches form VLSI 2021 technology highlights

The upcoming VLSI Symposia will feature a number of papers that show the ways in which novel approaches are going to be needed to continue scaling.
January 15, 2021

Copper’s future is troubled but it’s likely to stick around

The metal has done sterling service for 20 years but the time is approaching to find a replacement for copper as problems with parasitics continue to build up, work presented at last month’s IEDM shows. But it's not an obvious switch.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: , , , ,
December 18, 2020

Backside metal defends against IR drop and side-channel attacks

Work presented at IEDM 2020 shows taking advantage of the IC backside for power and ground for the additional area can deliver further benefits for IR drop and security.
November 9, 2020

IEDM 2020 highlights transistor and interconnect advances

This year's IEDM will feature papers that exploit stacked nanoribbons to reduce CMOS footprint, graphene interconnects that support easier integration, and the variability prospects of 2D semiconductors.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: , ,

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