Workshops on portable stimulus, functional safety, verification of RISC-V processors, and design with chiplets and large language models will feature at the upcoming 2024 DVCon US.
Arm has added machine-learning extensions and pointer-security instructions to its latest Cortex-M series core.
Cadence has linked several machine-learning approaches to build a tool that is designed to speed up the detection and diagnosis of on-chip power-integrity issues.
Imperas Software has worked with AI specialist Tenstorrent to create and distribute a model of the Ascalon processor core.
DVCon Europe has announced its two keynote presentations, focusing on energy-efficient high-performance computing and machine learning.
The recent Verification Futures Europe conference looked at what AI, from decision trees to foundation models, could do to speed up RTL checks.
At the recent VLSI Symposium, Google vice president Parthasarathy Ranganathan described the importance of co-design and the software stack in its data-center designs.
Semidynamics has released a customizable vector unit with out-of-order execution support to accompany its 64bit RISC-V processor cores.
A comprehensive review of ML's potential and its current use identifies challenges ahead.
Processor IP company will incorporate custom instructions and other changes in its superscalar core, which includes a novel memory unit for sparse matrices.
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