Heterogeneous integration has the potential to overcome the yield and cost challenges presented by the growing headwinds associated with process scaling. But it may take a dramatic rethink in design approaches.
Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
The US Quantum Economic Development Consortium is looking to stimulate a supply chain and technology infrastructure for quantum computing, with more about its efforts due to come out in the next few days.
The verification IP is the first to become commercially available for the bus interface backed by companies such as AMD, Google, IBM, Micron and Xilinx.
AI, its system design implications and its impact on EDA tools themselves will be a key theme for ES Design West next month.
Collaboration on DTCO offers IBM a better way to evaluate combinations of transistor architectures, materials and other process technology innovations using design metrics, before real wafers become available for physical experimentation.
Fifteen years on from the design gap that triggered the IP revolution, implementation costs have created a new one.
DAC in June will feature a series of keynotes and technical sessions on machine learning and AI for both target applications and in the design process itself.
Among the papers at this year's VLSI Symposia in Hawaii in June, Samsung will describe a 7nm CMOS process that uses EUV lithography to tighten up device features on minimum-pitch interconnects.
“It’s the time between putting out an open-source ARM core and getting a letter from an ARM lawyer,” says UC Berkeley professor Krste Asanovic. So, some design teams are turning to IP that started out as open source to provide more scope for experimentation.
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