EDA Topics
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Keep chip designs on the level with CMP simulation and dummy fill optimization
This case study shows how rising CMP simulation quality can be leveraged to detect the position and type of planarity hotspots before manufacture and verify the planarity of a layout.
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How to achieve accurate reset domain crossing verification
The authors describe an emerging methodology based on a hierarchical data model approach that satisfies the key requirements for RDC verification.
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How automated power/ground short checks slash time during implementation
Early detection using design integrity checks during implementation from abstract LEF/DEF inputs can deliver major efficiencies.
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How MaxLinear got faster signoff DRC while optimizing reliability and manufacturability
The RF and AMS specialist turned to design software that allowed it to run design checks during place and route.
DFM
DFT
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IC Implementation
Verification
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