EDA Topics
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How to achieve fast, automated, sign-off verification of DFM hotspot fixes in P&R
A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.
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UVM coding guidelines offer clarity in a complex world
These 13 suggestions toward best practice address some of the most persistent challenges with the Universal Verification Methodology.
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Keep chip designs on the level with CMP simulation and dummy fill optimization
This case study shows how rising CMP simulation quality can be leveraged to detect the position and type of planarity hotspots before manufacture and verify the planarity of a layout.
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How to achieve accurate reset domain crossing verification
The authors describe an emerging methodology based on a hierarchical data model approach that satisfies the key requirements for RDC verification.
DFM
DFT
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ESL
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IC Implementation
Verification
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