EDA Topics
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Addressing challenges in IC verification configuration
Invocation GUIs play an important role in delivering efficient verification runs. Learn how to take advantage of the features within Calibre Interactive.
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P&R filler cell insertion slowing you down? Replace it
A physical verification-ready flow can speed project delivery by making your use of filler cells more efficient.
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How to optimize test patterns based on critical area
The world of ATPG just changed with the introduction of a new way to create and choose the most effective test patterns.
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How to achieve fast, automated, sign-off verification of DFM hotspot fixes in P&R
A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.
DFM
DFT
- Article How to optimize test patterns based on critical area
- Expert Insight Catch the next wave in DFT automation
- Expert Insight How to gain a competitive edge with advanced DFT
ESL
- Expert Insight Take advantage of the automated refactoring of design and verification code
- Expert Insight High-level synthesis for AI: Part Two
- Expert Insight High-level synthesis for AI: Part One
IC Implementation
Verification
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