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June 16, 2020

Transistor stacks piled high at VLSI

As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , , , , ,   |  Organizations: ,
May 26, 2020

Nanometer scaling puts focus on power at VLSI in June

Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: , , , ,
May 23, 2018

Pillar transistor points to smaller SRAMs at 5nm

Imec and Unisantis Electronics have developed a process flow based on a vertical transistor with a gate on all sides they claim will lead to denser memories on a 5nm node.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:

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