GaN


May 26, 2020

Nanometer scaling puts focus on power at VLSI in June

Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: , , , ,
October 24, 2016

7nm finFET process techniques lead IEDM lineup

At the 62nd annual IEDM taking place in early December two of the leading groups in process development will take the wraps off their 7nm finFET technologies.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
December 15, 2015

GaN power makes progress at IEDM 2015

Researchers describe at IEDM 2015 how they are making gallium nitride fit into a wider range of power-handling applications and may even result in mass-market vertical transistors.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , ,   |  Organizations: ,
May 11, 2015

VLSI Symposia delve into future process choices

Intel 14nm finFET SoC process is among the highlights of the 2015 VLSI Symposia alongside research that looks at the integration of III-V and 2D materials for future processes.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , ,   |  Organizations: , , ,
August 8, 2014

Custom instrumentation helps build models for more advanced RF amplifiers

High peak-to-average ratios inherent in 4G/5G modulation schemes are driving the circuitry controlling RF PAs to become more modeling-oriented.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , , , , ,   |  Organizations:
February 27, 2012

System-level design meets power

In the world of power semiconductors, not many companies try to go fabless. The tradeoffs between design and process offer many more options for system-level design, argued Infineon's Reinhard Ploss at the ISS Europe conference.
Article  |  Topics: Commentary, Conferences, Blog - EDA  |  Tags: , , , , ,

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